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wdenkf4675562002-10-02 14:20:15 +00001/*
wdenk69141282003-07-07 20:07:54 +00002 * (C) Copyright 2000-2003
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf4675562002-10-02 14:20:15 +000043
wdenkfb229ae2003-08-07 22:18:11 +000044#define CONFIG_BOOTCOUNT_LIMIT
45
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000047
48#define CONFIG_BOARD_TYPES 1 /* support board types */
49
50#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
51
52#undef CONFIG_BOOTARGS
wdenk34b613e2002-12-17 01:51:00 +000053
54#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkfb229ae2003-08-07 22:18:11 +000055 "netdev=eth0\0" \
wdenk34b613e2002-12-17 01:51:00 +000056 "nfsargs=setenv bootargs root=/dev/nfs rw " \
57 "nfsroot=$(serverip):$(rootpath)\0" \
58 "ramargs=setenv bootargs root=/dev/ram rw\0" \
59 "addip=setenv bootargs $(bootargs) " \
60 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
61 ":$(hostname):$(netdev):off panic=1\0" \
62 "flash_nfs=run nfsargs addip;" \
63 "bootm $(kernel_addr)\0" \
64 "flash_self=run ramargs addip;" \
65 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
66 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
67 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenkec342722004-01-31 20:13:31 +000068 "bootfile=/tftpboot/TQM850L/uImage\0" \
wdenk34b613e2002-12-17 01:51:00 +000069 "kernel_addr=40040000\0" \
70 "ramdisk_addr=40100000\0" \
71 ""
72#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000073
74#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
75#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
76
77#undef CONFIG_WATCHDOG /* watchdog disabled */
78
79#define CONFIG_STATUS_LED 1 /* Status LED enabled */
80
81#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
82
83#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
84
85#define CONFIG_MAC_PARTITION
86#define CONFIG_DOS_PARTITION
87
88#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
89
90#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk34b613e2002-12-17 01:51:00 +000091 CFG_CMD_ASKENV | \
wdenkf4675562002-10-02 14:20:15 +000092 CFG_CMD_DHCP | \
93 CFG_CMD_IDE | \
94 CFG_CMD_DATE )
95
96/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
97#include <cmd_confdefs.h>
98
99/*
100 * Miscellaneous configurable options
101 */
102#define CFG_LONGHELP /* undef to save memory */
wdenk34b613e2002-12-17 01:51:00 +0000103#define CFG_PROMPT "=> " /* Monitor Command Prompt */
104
105#if 0
106#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
107#endif
108#ifdef CFG_HUSH_PARSER
109#define CFG_PROMPT_HUSH_PS2 "> "
110#endif
111
wdenkf4675562002-10-02 14:20:15 +0000112#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk34b613e2002-12-17 01:51:00 +0000113#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000114#else
wdenk34b613e2002-12-17 01:51:00 +0000115#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000116#endif
117#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenk34b613e2002-12-17 01:51:00 +0000118#define CFG_MAXARGS 16 /* max number of command args */
wdenkf4675562002-10-02 14:20:15 +0000119#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
120
121#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
122#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
123
124#define CFG_LOAD_ADDR 0x100000 /* default load address */
125
wdenk34b613e2002-12-17 01:51:00 +0000126#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf4675562002-10-02 14:20:15 +0000127
128#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
129
130/*
131 * Low Level Configuration Settings
132 * (address mappings, register initial values, etc.)
133 * You should know what you are doing if you make changes here.
134 */
135/*-----------------------------------------------------------------------
136 * Internal Memory Mapped Register
137 */
138#define CFG_IMMR 0xFFF00000
139
140/*-----------------------------------------------------------------------
141 * Definitions for initial stack pointer and data area (in DPRAM)
142 */
143#define CFG_INIT_RAM_ADDR CFG_IMMR
144#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
145#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
146#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
147#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
148
149/*-----------------------------------------------------------------------
150 * Start addresses for the final memory configuration
151 * (Set up by the startup code)
152 * Please note that CFG_SDRAM_BASE _must_ start at 0
153 */
154#define CFG_SDRAM_BASE 0x00000000
155#define CFG_FLASH_BASE 0x40000000
156#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
157#define CFG_MONITOR_BASE CFG_FLASH_BASE
158#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
159
160/*
161 * For booting Linux, the board info and command line data
162 * have to be in the first 8 MB of memory, since this is
163 * the maximum mapped by the Linux kernel during initialization.
164 */
165#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
166
167/*-----------------------------------------------------------------------
168 * FLASH organization
169 */
170#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenkeda42082003-01-17 16:27:01 +0000171#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000172
173#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
174#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
175
176#define CFG_ENV_IS_IN_FLASH 1
177#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
178#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
179
180/* Address and size of Redundant Environment Sector */
181#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
182#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
183
184/*-----------------------------------------------------------------------
185 * Hardware Information Block
186 */
187#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
188#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
189#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
190
191/*-----------------------------------------------------------------------
192 * Cache Configuration
193 */
194#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
195#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
196#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
197#endif
198
199/*-----------------------------------------------------------------------
200 * SYPCR - System Protection Control 11-9
201 * SYPCR can only be written once after reset!
202 *-----------------------------------------------------------------------
203 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
204 */
205#if defined(CONFIG_WATCHDOG)
206#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
207 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
208#else
209#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
210#endif
211
212/*-----------------------------------------------------------------------
213 * SIUMCR - SIU Module Configuration 11-6
214 *-----------------------------------------------------------------------
215 * PCMCIA config., multi-function pin tri-state
216 */
217#ifndef CONFIG_CAN_DRIVER
218#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
219#else /* we must activate GPL5 in the SIUMCR for CAN */
220#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
221#endif /* CONFIG_CAN_DRIVER */
222
223/*-----------------------------------------------------------------------
224 * TBSCR - Time Base Status and Control 11-26
225 *-----------------------------------------------------------------------
226 * Clear Reference Interrupt Status, Timebase freezing enabled
227 */
228#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
229
230/*-----------------------------------------------------------------------
231 * RTCSC - Real-Time Clock Status and Control Register 11-27
232 *-----------------------------------------------------------------------
233 */
234#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
235
236/*-----------------------------------------------------------------------
237 * PISCR - Periodic Interrupt Status and Control 11-31
238 *-----------------------------------------------------------------------
239 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
240 */
241#define CFG_PISCR (PISCR_PS | PISCR_PITF)
242
243/*-----------------------------------------------------------------------
244 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
245 *-----------------------------------------------------------------------
246 * Reset PLL lock status sticky bit, timer expired status bit and timer
247 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000248 */
wdenkf4675562002-10-02 14:20:15 +0000249#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000250
251/*-----------------------------------------------------------------------
252 * SCCR - System Clock and reset Control Register 15-27
253 *-----------------------------------------------------------------------
254 * Set clock output, timebase and RTC source and divider,
255 * power management and some other internal clocks
256 */
257#define SCCR_MASK SCCR_EBDF11
wdenkc78bf132004-04-24 23:23:30 +0000258#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000259 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
260 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000261
262/*-----------------------------------------------------------------------
263 * PCMCIA stuff
264 *-----------------------------------------------------------------------
265 *
266 */
267#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
268#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
269#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
270#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
271#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
272#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
273#define CFG_PCMCIA_IO_ADDR (0xEC000000)
274#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
275
276/*-----------------------------------------------------------------------
277 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
278 *-----------------------------------------------------------------------
279 */
280
281#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
282
283#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
284#undef CONFIG_IDE_LED /* LED for ide not supported */
285#undef CONFIG_IDE_RESET /* reset for ide not supported */
286
287#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
288#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
289
290#define CFG_ATA_IDE0_OFFSET 0x0000
291
292#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
293
294/* Offset for data I/O */
295#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
296
297/* Offset for normal register accesses */
298#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
299
300/* Offset for alternate registers */
301#define CFG_ATA_ALT_OFFSET 0x0100
302
wdenkf4675562002-10-02 14:20:15 +0000303/*-----------------------------------------------------------------------
304 *
305 *-----------------------------------------------------------------------
306 *
307 */
wdenkf4675562002-10-02 14:20:15 +0000308#define CFG_DER 0
309
310/*
311 * Init Memory Controller:
312 *
313 * BR0/1 and OR0/1 (FLASH)
314 */
315
316#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
317#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
318
319/* used to re-map FLASH both when starting from SRAM or FLASH:
320 * restrict access enough to keep SRAM working (if any)
321 * but not too much to meddle with FLASH accesses
322 */
323#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
324#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
325
326/*
327 * FLASH timing:
328 */
wdenkf4675562002-10-02 14:20:15 +0000329#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
330 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000331
332#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
333#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
334#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
335
336#define CFG_OR1_REMAP CFG_OR0_REMAP
337#define CFG_OR1_PRELIM CFG_OR0_PRELIM
338#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
339
340/*
341 * BR2/3 and OR2/3 (SDRAM)
342 *
343 */
344#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
345#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
346#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
347
348/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
349#define CFG_OR_TIMING_SDRAM 0x00000A00
350
351#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
352#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
353
354#ifndef CONFIG_CAN_DRIVER
355#define CFG_OR3_PRELIM CFG_OR2_PRELIM
356#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
357#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
358#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
359#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
360#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
361#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
362 BR_PS_8 | BR_MS_UPMB | BR_V )
363#endif /* CONFIG_CAN_DRIVER */
364
365/*
366 * Memory Periodic Timer Prescaler
367 *
368 * The Divider for PTA (refresh timer) configuration is based on an
369 * example SDRAM configuration (64 MBit, one bank). The adjustment to
370 * the number of chip selects (NCS) and the actually needed refresh
371 * rate is done by setting MPTPR.
372 *
373 * PTA is calculated from
374 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
375 *
376 * gclk CPU clock (not bus clock!)
377 * Trefresh Refresh cycle * 4 (four word bursts used)
378 *
379 * 4096 Rows from SDRAM example configuration
380 * 1000 factor s -> ms
381 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
382 * 4 Number of refresh cycles per period
383 * 64 Refresh cycle in ms per number of rows
384 * --------------------------------------------
385 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
386 *
387 * 50 MHz => 50.000.000 / Divider = 98
388 * 66 Mhz => 66.000.000 / Divider = 129
389 * 80 Mhz => 80.000.000 / Divider = 156
390 */
wdenkc78bf132004-04-24 23:23:30 +0000391
392#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
393#define CFG_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000394
395/*
396 * For 16 MBit, refresh rates could be 31.3 us
397 * (= 64 ms / 2K = 125 / quad bursts).
398 * For a simpler initialization, 15.6 us is used instead.
399 *
400 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
401 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
402 */
403#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
404#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
405
406/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
407#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
408#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
409
410/*
411 * MAMR settings for SDRAM
412 */
413
414/* 8 column SDRAM */
415#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
416 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
417 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
418/* 9 column SDRAM */
419#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
420 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
421 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
422
423
424/*
425 * Internal Definitions
426 *
427 * Boot Flags
428 */
429#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
430#define BOOTFLAG_WARM 0x02 /* Software reboot */
431
432#endif /* __CONFIG_H */