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git01.mediatek.com / filogic / uboot / 0191b3c5ef5c35dea7449acbd3fc052452227bda / . / include / configs / BAB7xx.h
blob: 5dd7a7e9f7c25ca2ed0ba48a33e8249e3c5e25df [file] [log] [blame]
wdenke2211742002-11-02 23:30:20 +0000[diff] [blame]1/*
2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#include <asm/processor.h>
32
33#undef DEBUG
34#define GTREGREAD(x) 0xffffffff /* needed for debug */
35
36/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41/* these hardware addresses are pretty bogus, please change them to
42 suit your needs */
43
44/* first ethernet */
45#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
46
47#define CONFIG_IPADDR 192.168.0.105
48#define CONFIG_SERVERIP 192.168.0.100
49
50#define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */
51
52#define CONFIG_BAUDRATE 9600 /* console baudrate */
53
54#undef CONFIG_WATCHDOG
55
56#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57
58#define CONFIG_ZERO_BOOTDELAY_CHECK
59
60#undef CONFIG_BOOTARGS
61#define CONFIG_BOOTCOMMAND \
62 "bootp 1000000; " \
63 "setenv bootargs root=ramfs console=ttyS00,9600 " \
64 "ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \
65 "$(netmask):$(hostname):eth0:none; " \
66 "bootm"
67
68#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
69#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
70
71#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
72
73#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]74 CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\
75 CFG_CMD_FDC | CFG_CMD_ELF)
wdenke2211742002-11-02 23:30:20 +0000[diff] [blame]76
77/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
78#include <cmd_confdefs.h>
79
80/*
81 * Miscellaneous configurable options
82 */
83#define CFG_LONGHELP /* undef to save memory */
84#define CFG_PROMPT "=> " /* Monitor Command Prompt */
85
86/*
87 * choose between COM1 and COM2 as serial console
88 */
89#define CONFIG_CONS_INDEX 1
90
91#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
92#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
93#else
94#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
95#endif
96#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
97#define CFG_MAXARGS 16 /* max number of command args */
98#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
99
100#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
101#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
102
103#define CFG_LOAD_ADDR 0x1000000 /* default load address */
104
105#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */
106
107#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
108
109/*
110 * Low Level Configuration Settings
111 * (address mappings, register initial values, etc.)
112 * You should know what you are doing if you make changes here.
113 */
114#define CFG_BOARD_ASM_INIT
115#define CONFIG_MISC_INIT_R
116
117/*
118 * Choose the address mapping scheme for the MPC106 mem controller.
119 * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
120 */
121#define CFG_ADDRESS_MAP_A
122#ifdef CFG_ADDRESS_MAP_A
123
124#define CFG_PCI_MEMORY_BUS 0x80000000
125#define CFG_PCI_MEMORY_PHYS 0x00000000
126#define CFG_PCI_MEMORY_SIZE 0x80000000
127
128#define CFG_PCI_MEM_BUS 0x00000000
129#define CFG_PCI_MEM_PHYS 0xc0000000
130#define CFG_PCI_MEM_SIZE 0x3f000000
131
132#define CFG_ISA_MEM_BUS 0
133#define CFG_ISA_MEM_PHYS 0
134#define CFG_ISA_MEM_SIZE 0
135
136#define CFG_PCI_IO_BUS 0x1000
137#define CFG_PCI_IO_PHYS 0x81000000
138#define CFG_PCI_IO_SIZE 0x01000000-CFG_PCI_IO_BUS
139
140#define CFG_ISA_IO_BUS 0x00000000
141#define CFG_ISA_IO_PHYS 0x80000000
142#define CFG_ISA_IO_SIZE 0x00800000
143
144#else
145
146#define CFG_PCI_MEMORY_BUS 0x00000000
147#define CFG_PCI_MEMORY_PHYS 0x00000000
148#define CFG_PCI_MEMORY_SIZE 0x40000000
149
150#define CFG_PCI_MEM_BUS 0x80000000
151#define CFG_PCI_MEM_PHYS 0x80000000
152#define CFG_PCI_MEM_SIZE 0x7d000000
153
154#define CFG_ISA_MEM_BUS 0x00000000
155#define CFG_ISA_MEM_PHYS 0xfd000000
156#define CFG_ISA_MEM_SIZE 0x01000000
157
158#define CFG_PCI_IO_BUS 0x00800000
159#define CFG_PCI_IO_PHYS 0xfe800000
160#define CFG_PCI_IO_SIZE 0x00400000
161
162#define CFG_ISA_IO_BUS 0x00000000
163#define CFG_ISA_IO_PHYS 0xfe000000
164#define CFG_ISA_IO_SIZE 0x00800000
165
166#endif /*CFG_ADDRESS_MAP_A */
167
168#define CFG_60X_PCI_MEM_OFFSET 0x00000000
169
170/* driver defines FDC,IDE,... */
171#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
172#define CFG_ISA_IO CFG_ISA_IO_PHYS
173#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
174
175/*
176 * Start addresses for the final memory configuration
177 * (Set up by the startup code)
178 * Please note that CFG_SDRAM_BASE _must_ start at 0
179 */
180#define CFG_SDRAM_BASE 0x00000000
181#define CFG_FLASH_BASE 0xfff00000
182
183/*
184 * Definitions for initial stack pointer and data area
185 */
186#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
187#define CFG_INIT_RAM_END 0x4000
188#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
189#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
190#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
191
192/*
193 * Flash mapping/organization on the MPC10x.
194 */
195#define FLASH_BASE0_PRELIM 0xff800000
196#define FLASH_BASE1_PRELIM 0xffc00000
197
198#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
199#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
200
201#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
202#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
203
204#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
205#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
206
207#define CFG_MONITOR_BASE CFG_FLASH_BASE
208#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
209#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
210#undef CFG_MEMTEST
211
212/*
213 * Environment settings
214 */
215#define CONFIG_ENV_OVERWRITE
216#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
217#define CFG_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
218#define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
219/*
220 * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
221 * user applications can use the remaining space for other purposes.
222 */
223#define CFG_ENV_ADDR (CFG_NVRAM_SIZE +0x10 -0x800)
224#define CFG_NV_SROM_COPY_ADDR (CFG_NVRAM_SIZE +0x10 -0x400)
225#define CFG_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */
226#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
227
228/*
229 * Serial devices
230 */
231#define CFG_NS16550
232#define CFG_NS16550_SERIAL
233#define CFG_NS16550_REG_SIZE 1
234#define CFG_NS16550_CLK 1843200
235#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
236#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
237
238/*
239 * PCI stuff
240 */
241#define CONFIG_PCI /* include pci support */
242#define CONFIG_PCI_PNP /* pci plug-and-play */
243#define CONFIG_PCI_HOST PCI_HOST_AUTO
244#undef CONFIG_PCI_SCAN_SHOW
245
246/*
247 * Video console (graphic: SMI LynxEM, keyboard: i8042)
248 */
249#define CONFIG_VIDEO
250#define CONFIG_CFB_CONSOLE
251#define CONFIG_VIDEO_SMI_LYNXEM
252#define CONFIG_I8042_KBD
253#define CONFIG_VIDEO_LOGO
254#define CONFIG_CONSOLE_TIME
255#define CONFIG_CONSOLE_EXTRA_INFO
256#define CONFIG_CONSOLE_CURSOR
257#define CFG_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */
258
259/*
260 * IDE/SCSI globals
261 */
262#ifndef __ASSEMBLY__
263extern unsigned int eltec_board;
264extern unsigned int ata_reset_time;
265extern unsigned int scsi_reset_time;
266extern unsigned short scsi_dev_id;
267extern unsigned int scsi_max_scsi_id;
268extern unsigned char scsi_sym53c8xx_ccf;
269#endif
270
271/*
272 * ATAPI Support (experimental)
273 */
274#define CONFIG_ATAPI
275#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
276#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
277
278#define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */
279#define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */
280#define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
281#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
282#define CFG_ATA_REG_OFFSET 0 /* reg offset */
283#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
284
285#define ATA_RESET_TIME (ata_reset_time)
286
287#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
288#undef CONFIG_IDE_LED /* no led for ide supported */
289
290/*
291 * SCSI support (experimental) only SYM53C8xx supported
292 */
293#define CONFIG_SCSI_SYM53C8XX
294#define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */
295#define CFG_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */
296#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
297#define CFG_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */
298#define CFG_SCSI_MAX_DEVICE (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */
299#define CFG_SCSI_SPIN_UP_TIME (scsi_reset_time)
300
301/*
302 * Partion suppport
303 */
304#define CONFIG_DOS_PARTITION
305#define CONFIG_MAC_PARTITION
306#define CONFIG_ISO_PARTITION
307
308/*
309 * Winbond Configuration
310 */
311#define CFG_WINBOND_83C553 1 /* has a winbond bridge */
312#define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */
313#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */
314#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */
315
316/*
317 * NS87308 Configuration
318 */
319#define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */
320#define CFG_NS87308_BADDR_10 1
321#define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]322 CFG_NS87308_UART2 | \
323 CFG_NS87308_KBC1 | \
324 CFG_NS87308_MOUSE | \
325 CFG_NS87308_FDC | \
326 CFG_NS87308_RARP | \
327 CFG_NS87308_GPIO | \
328 CFG_NS87308_POWRMAN | \
329 CFG_NS87308_RTC_APC )
wdenke2211742002-11-02 23:30:20 +0000[diff] [blame]330
331#define CFG_NS87308_PS2MOD
332#define CFG_NS87308_GPIO_BASE 0x0220
333#define CFG_NS87308_PWMAN_BASE 0x0460
334#define CFG_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */
335
336/*
337 * set up the NVRAM access registers
338 * NVRAM's controlled by the configurable CS line from the 87308
339 */
340#define CFG_NS87308_CS0_BASE 0x0076
341#define CFG_NS87308_CS0_CONF 0x40
342#define CFG_NS87308_CS1_BASE 0x0070
343#define CFG_NS87308_CS1_CONF 0x1C
344#define CFG_NS87308_CS2_BASE 0x0071
345#define CFG_NS87308_CS2_CONF 0x1C
346
347#define CONFIG_RTC_MK48T59
348
349/*
350 * Initial BATs
351 */
352#if 1
353
354#define CFG_IBAT0L 0
355#define CFG_IBAT0U 0
356#define CFG_DBAT0L CFG_IBAT1L
357#define CFG_DBAT0U CFG_IBAT1U
358
359#define CFG_IBAT1L 0
360#define CFG_IBAT1U 0
361#define CFG_DBAT1L CFG_IBAT1L
362#define CFG_DBAT1U CFG_IBAT1U
363
364#define CFG_IBAT2L 0
365#define CFG_IBAT2U 0
366#define CFG_DBAT2L CFG_IBAT2L
367#define CFG_DBAT2U CFG_IBAT2U
368
369#define CFG_IBAT3L 0
370#define CFG_IBAT3U 0
371#define CFG_DBAT3L CFG_IBAT3L
372#define CFG_DBAT3U CFG_IBAT3U
373
374#else
375
376/* SDRAM */
377#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
378#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
379#define CFG_DBAT0L CFG_IBAT1L
380#define CFG_DBAT0U CFG_IBAT1U
381
382/* address range for flashes */
383#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
384#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
385#define CFG_DBAT1L CFG_IBAT1L
386#define CFG_DBAT1U CFG_IBAT1U
387
388/* ISA IO space */
389#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
390#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
391#define CFG_DBAT2L CFG_IBAT2L
392#define CFG_DBAT2U CFG_IBAT2U
393
394/* ISA memory space */
395#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
396#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
397#define CFG_DBAT3L CFG_IBAT3L
398#define CFG_DBAT3U CFG_IBAT3U
399
400#endif
401
402/*
403 * Speed settings are board specific
404 */
405#ifndef __ASSEMBLY__
406extern unsigned long bab7xx_get_bus_freq (void);
407extern unsigned long bab7xx_get_gclk_freq (void);
408#endif
409#define CFG_BUS_HZ bab7xx_get_bus_freq()
410#define CFG_BUS_CLK CFG_BUS_HZ
411#define CFG_CPU_CLK bab7xx_get_gclk_freq()
412
413/*
414 * For booting Linux, the board info and command line data
415 * have to be in the first 8 MB of memory, since this is
416 * the maximum mapped by the Linux kernel during initialization.
417 */
418#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
419
420/*
421 * Cache Configuration
422 */
423#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
424#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
425#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
426#endif
427
428/*
429 * L2 Cache Configuration is board specific for BAB740/BAB750
430 * Init values read from revision srom.
431 */
432#undef CFG_L2
433#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]434 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
wdenke2211742002-11-02 23:30:20 +0000[diff] [blame]435#define L2_ENABLE (L2_INIT | L2CR_L2E)
436
437#define CFG_L2_BAB7xx
438
439/*
440 * Internal Definitions
441 *
442 * Boot Flags
443 */
444#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
445#define BOOTFLAG_WARM 0x02 /* Software reboot */
446
447
448#define CONFIG_NET_MULTI /* Multi ethernet cards support */
449#define CONFIG_TULIP
450#define CONFIG_TULIP_SELECT_MEDIA
451
452#endif /* __CONFIG_H */