Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2001 Navin Boppuri / Prashant Patel |
| 4 | * <nboppuri@trinetcommunication.com>, |
| 5 | * <pmpatel@trinetcommunication.com> |
| 6 | * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de> |
| 7 | * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>. |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * MPC8xx CPM SPI interface. |
| 12 | * |
| 13 | * Parts of this code are probably not portable and/or specific to |
| 14 | * the board which I used for the tests. Please send fixes/complaints |
| 15 | * to wd@denx.de |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #include <common.h> |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 20 | #include <dm.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 21 | #include <mpc8xx.h> |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 22 | #include <spi.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 23 | #include <linux/delay.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 24 | |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 25 | #include <asm/cpm_8xx.h> |
| 26 | #include <asm/io.h> |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 27 | #include <asm/gpio.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 28 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 29 | #define CPM_SPI_BASE_RX CPM_SPI_BASE |
| 30 | #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t)) |
| 31 | |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 32 | #define MAX_BUFFER 0x104 |
| 33 | |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 34 | struct mpc8xx_priv { |
| 35 | spi_t __iomem *spi; |
| 36 | struct gpio_desc gpios[16]; |
| 37 | int max_cs; |
| 38 | }; |
| 39 | |
| 40 | static int mpc8xx_spi_set_mode(struct udevice *dev, uint mod) |
| 41 | { |
| 42 | return 0; |
| 43 | } |
| 44 | |
| 45 | static int mpc8xx_spi_set_speed(struct udevice *dev, uint speed) |
| 46 | { |
| 47 | return 0; |
| 48 | } |
| 49 | |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 50 | static int mpc8xx_spi_probe(struct udevice *dev) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 51 | { |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 52 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 53 | cpm8xx_t __iomem *cp = &immr->im_cpm; |
| 54 | spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; |
| 55 | cbd_t __iomem *tbdf, *rbdf; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 56 | |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 57 | /* Disable relocation */ |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 58 | out_be16(&spi->spi_rpbase, 0x1d80); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 59 | |
| 60 | /* 1 */ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 61 | /* Initialize the parameter ram. |
| 62 | * We need to make sure many things are initialized to zero |
| 63 | */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 64 | out_be32(&spi->spi_rstate, 0); |
| 65 | out_be32(&spi->spi_rdp, 0); |
| 66 | out_be16(&spi->spi_rbptr, 0); |
| 67 | out_be16(&spi->spi_rbc, 0); |
| 68 | out_be32(&spi->spi_rxtmp, 0); |
| 69 | out_be32(&spi->spi_tstate, 0); |
| 70 | out_be32(&spi->spi_tdp, 0); |
| 71 | out_be16(&spi->spi_tbptr, 0); |
| 72 | out_be16(&spi->spi_tbc, 0); |
| 73 | out_be32(&spi->spi_txtmp, 0); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 74 | |
| 75 | /* 3 */ |
| 76 | /* Set up the SPI parameters in the parameter ram */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 77 | out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX); |
| 78 | out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 79 | |
| 80 | /***********IMPORTANT******************/ |
| 81 | |
| 82 | /* |
| 83 | * Setting transmit and receive buffer descriptor pointers |
| 84 | * initially to rbase and tbase. Only the microcode patches |
| 85 | * documentation talks about initializing this pointer. This |
| 86 | * is missing from the sample I2C driver. If you dont |
| 87 | * initialize these pointers, the kernel hangs. |
| 88 | */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 89 | out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX); |
| 90 | out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 91 | |
| 92 | /* 4 */ |
| 93 | /* Init SPI Tx + Rx Parameters */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 94 | while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 95 | ; |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 96 | |
| 97 | out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | |
| 98 | CPM_CR_FLG); |
| 99 | while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 100 | ; |
| 101 | |
| 102 | /* 5 */ |
| 103 | /* Set SDMA configuration register */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 104 | out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 105 | |
| 106 | /* 6 */ |
| 107 | /* Set to big endian. */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 108 | out_8(&spi->spi_tfcr, SMC_EB); |
| 109 | out_8(&spi->spi_rfcr, SMC_EB); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 110 | |
| 111 | /* 7 */ |
| 112 | /* Set maximum receive size. */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 113 | out_be16(&spi->spi_mrblr, MAX_BUFFER); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 114 | |
| 115 | /* 8 + 9 */ |
| 116 | /* tx and rx buffer descriptors */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 117 | tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; |
| 118 | rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 119 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 120 | clrbits_be16(&tbdf->cbd_sc, BD_SC_READY); |
| 121 | clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 122 | |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 123 | /* 10 + 11 */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 124 | out_8(&cp->cp_spim, 0); /* Mask all SPI events */ |
| 125 | out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 126 | |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 127 | return 0; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 128 | } |
| 129 | |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 130 | static void mpc8xx_spi_cs_activate(struct udevice *dev) |
| 131 | { |
| 132 | struct mpc8xx_priv *priv = dev_get_priv(dev->parent); |
| 133 | struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev); |
| 134 | |
| 135 | dm_gpio_set_value(&priv->gpios[platdata->cs], 1); |
| 136 | } |
| 137 | |
| 138 | static void mpc8xx_spi_cs_deactivate(struct udevice *dev) |
| 139 | { |
| 140 | struct mpc8xx_priv *priv = dev_get_priv(dev->parent); |
| 141 | struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev); |
| 142 | |
| 143 | dm_gpio_set_value(&priv->gpios[platdata->cs], 0); |
| 144 | } |
| 145 | |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 146 | static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 147 | const void *dout, void *din, unsigned long flags) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 148 | { |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 149 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 150 | cpm8xx_t __iomem *cp = &immr->im_cpm; |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 151 | cbd_t __iomem *tbdf, *rbdf; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 152 | int tm; |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 153 | size_t count = (bitlen + 7) / 8; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 154 | |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 155 | if (count > MAX_BUFFER) |
| 156 | return -EINVAL; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 157 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 158 | tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; |
| 159 | rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 160 | |
| 161 | /* Set CS for device */ |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 162 | if (flags & SPI_XFER_BEGIN) |
| 163 | mpc8xx_spi_cs_activate(dev); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 164 | |
| 165 | /* Setting tx bd status and data length */ |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 166 | out_be32(&tbdf->cbd_bufaddr, (ulong)dout); |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 167 | out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); |
| 168 | out_be16(&tbdf->cbd_datlen, count); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 169 | |
| 170 | /* Setting rx bd status and data length */ |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 171 | out_be32(&rbdf->cbd_bufaddr, (ulong)din); |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 172 | out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); |
| 173 | out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 174 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 175 | clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR | |
| 176 | SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8)); |
| 177 | out_8(&cp->cp_spim, 0); /* Mask all SPI events */ |
| 178 | out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 179 | |
| 180 | /* start spi transfer */ |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 181 | setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 182 | |
| 183 | /* -------------------------------- |
| 184 | * Wait for SPI transmit to get out |
| 185 | * or time out (1 second = 1000 ms) |
| 186 | * -------------------------------- */ |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 187 | for (tm = 0; tm < 1000; ++tm) { |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 188 | if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 189 | break; |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 190 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 191 | if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 192 | break; |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 193 | udelay(1000); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 194 | } |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 195 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 196 | if (tm >= 1000) |
| 197 | printf("*** spi_xfer: Time out while xferring to/from SPI!\n"); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 198 | |
| 199 | /* Clear CS for device */ |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 200 | if (flags & SPI_XFER_END) |
| 201 | mpc8xx_spi_cs_deactivate(dev); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 202 | |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 203 | return 0; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 204 | } |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 205 | |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 206 | static int mpc8xx_spi_ofdata_to_platdata(struct udevice *dev) |
| 207 | { |
| 208 | struct mpc8xx_priv *priv = dev_get_priv(dev); |
| 209 | int ret; |
| 210 | |
| 211 | ret = gpio_request_list_by_name(dev, "gpios", priv->gpios, |
| 212 | ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT); |
| 213 | if (ret < 0) |
| 214 | return ret; |
| 215 | |
| 216 | priv->max_cs = ret; |
| 217 | |
| 218 | return 0; |
| 219 | } |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 220 | static const struct dm_spi_ops mpc8xx_spi_ops = { |
| 221 | .xfer = mpc8xx_spi_xfer, |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 222 | .set_speed = mpc8xx_spi_set_speed, |
| 223 | .set_mode = mpc8xx_spi_set_mode, |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 224 | }; |
| 225 | |
| 226 | static const struct udevice_id mpc8xx_spi_ids[] = { |
| 227 | { .compatible = "fsl,mpc8xx-spi" }, |
| 228 | { } |
| 229 | }; |
| 230 | |
| 231 | U_BOOT_DRIVER(mpc8xx_spi) = { |
| 232 | .name = "mpc8xx_spi", |
| 233 | .id = UCLASS_SPI, |
| 234 | .of_match = mpc8xx_spi_ids, |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 235 | .of_to_plat = mpc8xx_spi_ofdata_to_platdata, |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 236 | .ops = &mpc8xx_spi_ops, |
| 237 | .probe = mpc8xx_spi_probe, |
Christophe Leroy | f4ced3c | 2022-10-14 09:14:44 +0200 | [diff] [blame] | 238 | .priv_auto = sizeof(struct mpc8xx_priv), |
Christophe Leroy | 996f235 | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 239 | }; |