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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Christophe Leroy069fa832017-07-06 10:23:22 +02002/*
3 * Copyright (c) 2001 Navin Boppuri / Prashant Patel
4 * <nboppuri@trinetcommunication.com>,
5 * <pmpatel@trinetcommunication.com>
6 * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
7 * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
Christophe Leroy069fa832017-07-06 10:23:22 +02008 */
9
10/*
11 * MPC8xx CPM SPI interface.
12 *
13 * Parts of this code are probably not portable and/or specific to
14 * the board which I used for the tests. Please send fixes/complaints
15 * to wd@denx.de
16 *
17 */
18
19#include <common.h>
Christophe Leroy996f2352018-11-21 08:51:57 +000020#include <dm.h>
Christophe Leroy069fa832017-07-06 10:23:22 +020021#include <mpc8xx.h>
Christophe Leroy996f2352018-11-21 08:51:57 +000022#include <spi.h>
Simon Glassdbd79542020-05-10 11:40:11 -060023#include <linux/delay.h>
Christophe Leroy069fa832017-07-06 10:23:22 +020024
Christophe Leroy996f2352018-11-21 08:51:57 +000025#include <asm/cpm_8xx.h>
26#include <asm/io.h>
Christophe Leroyf4ced3c2022-10-14 09:14:44 +020027#include <asm/gpio.h>
Christophe Leroy069fa832017-07-06 10:23:22 +020028
Christophe Leroy394f9b32017-07-06 10:33:13 +020029#define CPM_SPI_BASE_RX CPM_SPI_BASE
30#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
31
Christophe Leroy069fa832017-07-06 10:23:22 +020032#define MAX_BUFFER 0x104
33
Christophe Leroyf4ced3c2022-10-14 09:14:44 +020034struct mpc8xx_priv {
35 spi_t __iomem *spi;
36 struct gpio_desc gpios[16];
37 int max_cs;
38};
39
40static int mpc8xx_spi_set_mode(struct udevice *dev, uint mod)
41{
42 return 0;
43}
44
45static int mpc8xx_spi_set_speed(struct udevice *dev, uint speed)
46{
47 return 0;
48}
49
Christophe Leroy996f2352018-11-21 08:51:57 +000050static int mpc8xx_spi_probe(struct udevice *dev)
Christophe Leroy069fa832017-07-06 10:23:22 +020051{
Christophe Leroy394f9b32017-07-06 10:33:13 +020052 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
53 cpm8xx_t __iomem *cp = &immr->im_cpm;
54 spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
55 cbd_t __iomem *tbdf, *rbdf;
Christophe Leroy069fa832017-07-06 10:23:22 +020056
Christophe Leroy069fa832017-07-06 10:23:22 +020057 /* Disable relocation */
Christophe Leroyf4ced3c2022-10-14 09:14:44 +020058 out_be16(&spi->spi_rpbase, 0x1d80);
Christophe Leroy069fa832017-07-06 10:23:22 +020059
60/* 1 */
Christophe Leroy069fa832017-07-06 10:23:22 +020061 /* Initialize the parameter ram.
62 * We need to make sure many things are initialized to zero
63 */
Christophe Leroy394f9b32017-07-06 10:33:13 +020064 out_be32(&spi->spi_rstate, 0);
65 out_be32(&spi->spi_rdp, 0);
66 out_be16(&spi->spi_rbptr, 0);
67 out_be16(&spi->spi_rbc, 0);
68 out_be32(&spi->spi_rxtmp, 0);
69 out_be32(&spi->spi_tstate, 0);
70 out_be32(&spi->spi_tdp, 0);
71 out_be16(&spi->spi_tbptr, 0);
72 out_be16(&spi->spi_tbc, 0);
73 out_be32(&spi->spi_txtmp, 0);
Christophe Leroy069fa832017-07-06 10:23:22 +020074
75/* 3 */
76 /* Set up the SPI parameters in the parameter ram */
Christophe Leroy394f9b32017-07-06 10:33:13 +020077 out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
78 out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
Christophe Leroy069fa832017-07-06 10:23:22 +020079
80 /***********IMPORTANT******************/
81
82 /*
83 * Setting transmit and receive buffer descriptor pointers
84 * initially to rbase and tbase. Only the microcode patches
85 * documentation talks about initializing this pointer. This
86 * is missing from the sample I2C driver. If you dont
87 * initialize these pointers, the kernel hangs.
88 */
Christophe Leroy394f9b32017-07-06 10:33:13 +020089 out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
90 out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
Christophe Leroy069fa832017-07-06 10:23:22 +020091
92/* 4 */
93 /* Init SPI Tx + Rx Parameters */
Christophe Leroy394f9b32017-07-06 10:33:13 +020094 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
Christophe Leroy069fa832017-07-06 10:23:22 +020095 ;
Christophe Leroy394f9b32017-07-06 10:33:13 +020096
97 out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
98 CPM_CR_FLG);
99 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
Christophe Leroy069fa832017-07-06 10:23:22 +0200100 ;
101
102/* 5 */
103 /* Set SDMA configuration register */
Christophe Leroy394f9b32017-07-06 10:33:13 +0200104 out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
Christophe Leroy069fa832017-07-06 10:23:22 +0200105
106/* 6 */
107 /* Set to big endian. */
Christophe Leroy394f9b32017-07-06 10:33:13 +0200108 out_8(&spi->spi_tfcr, SMC_EB);
109 out_8(&spi->spi_rfcr, SMC_EB);
Christophe Leroy069fa832017-07-06 10:23:22 +0200110
111/* 7 */
112 /* Set maximum receive size. */
Christophe Leroy394f9b32017-07-06 10:33:13 +0200113 out_be16(&spi->spi_mrblr, MAX_BUFFER);
Christophe Leroy069fa832017-07-06 10:23:22 +0200114
115/* 8 + 9 */
116 /* tx and rx buffer descriptors */
Christophe Leroy394f9b32017-07-06 10:33:13 +0200117 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
118 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
Christophe Leroy069fa832017-07-06 10:23:22 +0200119
Christophe Leroy394f9b32017-07-06 10:33:13 +0200120 clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
121 clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
Christophe Leroy069fa832017-07-06 10:23:22 +0200122
Christophe Leroy069fa832017-07-06 10:23:22 +0200123/* 10 + 11 */
Christophe Leroy394f9b32017-07-06 10:33:13 +0200124 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
125 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
Christophe Leroy069fa832017-07-06 10:23:22 +0200126
Christophe Leroy996f2352018-11-21 08:51:57 +0000127 return 0;
Christophe Leroy069fa832017-07-06 10:23:22 +0200128}
129
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200130static void mpc8xx_spi_cs_activate(struct udevice *dev)
131{
132 struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
133 struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
134
135 dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
136}
137
138static void mpc8xx_spi_cs_deactivate(struct udevice *dev)
139{
140 struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
141 struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
142
143 dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
144}
145
Christophe Leroy996f2352018-11-21 08:51:57 +0000146static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
147 const void *dout, void *din, unsigned long flags)
Christophe Leroy069fa832017-07-06 10:23:22 +0200148{
Christophe Leroy394f9b32017-07-06 10:33:13 +0200149 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
150 cpm8xx_t __iomem *cp = &immr->im_cpm;
Christophe Leroy394f9b32017-07-06 10:33:13 +0200151 cbd_t __iomem *tbdf, *rbdf;
Christophe Leroy069fa832017-07-06 10:23:22 +0200152 int tm;
Christophe Leroy996f2352018-11-21 08:51:57 +0000153 size_t count = (bitlen + 7) / 8;
Christophe Leroy069fa832017-07-06 10:23:22 +0200154
Christophe Leroy996f2352018-11-21 08:51:57 +0000155 if (count > MAX_BUFFER)
156 return -EINVAL;
Christophe Leroy069fa832017-07-06 10:23:22 +0200157
Christophe Leroy394f9b32017-07-06 10:33:13 +0200158 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
159 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
Christophe Leroy069fa832017-07-06 10:23:22 +0200160
161 /* Set CS for device */
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200162 if (flags & SPI_XFER_BEGIN)
163 mpc8xx_spi_cs_activate(dev);
Christophe Leroy069fa832017-07-06 10:23:22 +0200164
165 /* Setting tx bd status and data length */
Christophe Leroy996f2352018-11-21 08:51:57 +0000166 out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
Christophe Leroy394f9b32017-07-06 10:33:13 +0200167 out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
168 out_be16(&tbdf->cbd_datlen, count);
Christophe Leroy069fa832017-07-06 10:23:22 +0200169
170 /* Setting rx bd status and data length */
Christophe Leroy996f2352018-11-21 08:51:57 +0000171 out_be32(&rbdf->cbd_bufaddr, (ulong)din);
Christophe Leroy394f9b32017-07-06 10:33:13 +0200172 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
173 out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
Christophe Leroy069fa832017-07-06 10:23:22 +0200174
Christophe Leroy394f9b32017-07-06 10:33:13 +0200175 clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
176 SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
177 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
178 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
Christophe Leroy069fa832017-07-06 10:23:22 +0200179
180 /* start spi transfer */
Christophe Leroy394f9b32017-07-06 10:33:13 +0200181 setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
Christophe Leroy069fa832017-07-06 10:23:22 +0200182
183 /* --------------------------------
184 * Wait for SPI transmit to get out
185 * or time out (1 second = 1000 ms)
186 * -------------------------------- */
Christophe Leroy48f896d2017-07-06 10:33:17 +0200187 for (tm = 0; tm < 1000; ++tm) {
Christophe Leroy394f9b32017-07-06 10:33:13 +0200188 if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
Christophe Leroy069fa832017-07-06 10:23:22 +0200189 break;
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200190
Christophe Leroy394f9b32017-07-06 10:33:13 +0200191 if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
Christophe Leroy069fa832017-07-06 10:23:22 +0200192 break;
Christophe Leroy48f896d2017-07-06 10:33:17 +0200193 udelay(1000);
Christophe Leroy069fa832017-07-06 10:23:22 +0200194 }
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200195
Christophe Leroy48f896d2017-07-06 10:33:17 +0200196 if (tm >= 1000)
197 printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
Christophe Leroy069fa832017-07-06 10:23:22 +0200198
199 /* Clear CS for device */
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200200 if (flags & SPI_XFER_END)
201 mpc8xx_spi_cs_deactivate(dev);
Christophe Leroy069fa832017-07-06 10:23:22 +0200202
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200203 return 0;
Christophe Leroy069fa832017-07-06 10:23:22 +0200204}
Christophe Leroy996f2352018-11-21 08:51:57 +0000205
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200206static int mpc8xx_spi_ofdata_to_platdata(struct udevice *dev)
207{
208 struct mpc8xx_priv *priv = dev_get_priv(dev);
209 int ret;
210
211 ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
212 ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT);
213 if (ret < 0)
214 return ret;
215
216 priv->max_cs = ret;
217
218 return 0;
219}
Christophe Leroy996f2352018-11-21 08:51:57 +0000220static const struct dm_spi_ops mpc8xx_spi_ops = {
221 .xfer = mpc8xx_spi_xfer,
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200222 .set_speed = mpc8xx_spi_set_speed,
223 .set_mode = mpc8xx_spi_set_mode,
Christophe Leroy996f2352018-11-21 08:51:57 +0000224};
225
226static const struct udevice_id mpc8xx_spi_ids[] = {
227 { .compatible = "fsl,mpc8xx-spi" },
228 { }
229};
230
231U_BOOT_DRIVER(mpc8xx_spi) = {
232 .name = "mpc8xx_spi",
233 .id = UCLASS_SPI,
234 .of_match = mpc8xx_spi_ids,
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200235 .of_to_plat = mpc8xx_spi_ofdata_to_platdata,
Christophe Leroy996f2352018-11-21 08:51:57 +0000236 .ops = &mpc8xx_spi_ops,
237 .probe = mpc8xx_spi_probe,
Christophe Leroyf4ced3c2022-10-14 09:14:44 +0200238 .priv_auto = sizeof(struct mpc8xx_priv),
Christophe Leroy996f2352018-11-21 08:51:57 +0000239};