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git01.mediatek.com / filogic / uboot / 0171144935ee59773fa3560bb060f9d44f6311fc / . / arch / arm / dts / stm32mp15xx-dhcor-u-boot.dtsi
blob: 08439342cb28e706690f81e150b0ae53cba4d268 [file] [log] [blame]
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright : STMicroelectronics 2018
4 *
5 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]7 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]8 */
9
10#include <dt-bindings/clock/stm32mp1-clksrc.h>
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]11#include "stm32mp15-u-boot.dtsi"
Marek Vasut272198e2020-04-29 15:08:38 +0200[diff] [blame]12#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
13#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
14#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
Marek Vasut01711442024-10-05 03:15:50 +0200[diff] [blame^]15#include "stm32mp15xx-dhsom-u-boot.dtsi"
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]16
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]17/ {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-all;
Marek Vasut8b08dfb2021-12-30 23:46:46 +0100[diff] [blame]19
20 aliases {
21 eeprom0 = &eeprom0;
22 };
23
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]24 config {
Marek Vasut39221b52020-04-22 13:18:14 +0200[diff] [blame]25 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]26 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
27 };
28};
29
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]30&flash0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Patrick Delaunayf172bcb2023-06-08 17:16:48 +0200[diff] [blame]32
33 partitions {
34 compatible = "fixed-partitions";
35 #address-cells = <1>;
36 #size-cells = <1>;
37
38 partition@0 {
39 label = "fsbl1";
40 reg = <0x00000000 0x00040000>;
41 };
42 partition@40000 {
43 label = "fsbl2";
44 reg = <0x00040000 0x00040000>;
45 };
Patrice Chotard0f2f0d52024-03-08 14:50:08 +0100[diff] [blame]46 partition@80000 {
Patrick Delaunayf172bcb2023-06-08 17:16:48 +0200[diff] [blame]47 label = "uboot";
48 reg = <0x00080000 0x00160000>;
49 };
Patrice Chotard0f2f0d52024-03-08 14:50:08 +0100[diff] [blame]50 partition@1e0000 {
Patrick Delaunayf172bcb2023-06-08 17:16:48 +0200[diff] [blame]51 label = "env1";
52 reg = <0x001E0000 0x00010000>;
53 };
Patrice Chotard0f2f0d52024-03-08 14:50:08 +0100[diff] [blame]54 partition@1f0000 {
Patrick Delaunayf172bcb2023-06-08 17:16:48 +0200[diff] [blame]55 label = "env2";
56 reg = <0x001F0000 0x00010000>;
57 };
58 };
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]59};
60
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]61&i2c4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-all;
63 bootph-pre-ram;
Marek Vasut8b08dfb2021-12-30 23:46:46 +0100[diff] [blame]64
65 eeprom0: eeprom@53 {
66 };
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]67};
68
69&i2c4_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]71 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]73 };
74};
75
76&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-all;
78 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]79
80 regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]82 };
83};
84
85&pwr_regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]87};
88
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]89&qspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]91};
92
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]93&qspi_clk_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]95 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]97 };
98};
99
100&qspi_bk1_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Marek Vasut3f3375c2023-10-10 01:15:51 +0200[diff] [blame]102 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]104 };
Marek Vasut3f3375c2023-10-10 01:15:51 +0200[diff] [blame]105};
106
107&qspi_cs1_pins_a {
108 bootph-pre-ram;
109 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]111 };
112};
113
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]114&rcc {
115 st,clksrc = <
116 CLK_MPU_PLL1P
117 CLK_AXI_PLL2P
118 CLK_MCU_PLL3P
119 CLK_PLL12_HSE
120 CLK_PLL3_HSE
121 CLK_PLL4_HSE
122 CLK_RTC_LSE
123 CLK_MCO1_DISABLED
124 CLK_MCO2_DISABLED
125 >;
126
127 st,clkdiv = <
128 1 /*MPU*/
129 0 /*AXI*/
130 0 /*MCU*/
131 1 /*APB1*/
132 1 /*APB2*/
133 1 /*APB3*/
134 1 /*APB4*/
135 2 /*APB5*/
136 23 /*RTC*/
137 0 /*MCO1*/
138 0 /*MCO2*/
139 >;
140
141 st,pkcs = <
142 CLK_CKPER_HSE
143 CLK_FMC_ACLK
144 CLK_QSPI_ACLK
145 CLK_ETH_DISABLED
146 CLK_SDMMC12_PLL4P
147 CLK_DSI_DSIPLL
148 CLK_STGEN_HSE
149 CLK_USBPHY_HSE
150 CLK_SPI2S1_PLL3Q
151 CLK_SPI2S23_PLL3Q
152 CLK_SPI45_HSI
153 CLK_SPI6_HSI
154 CLK_I2C46_HSI
155 CLK_SDMMC3_PLL4P
156 CLK_USBO_USBPHY
157 CLK_ADC_CKPER
158 CLK_CEC_LSE
159 CLK_I2C12_HSI
160 CLK_I2C35_HSI
161 CLK_UART1_HSI
162 CLK_UART24_HSI
163 CLK_UART35_HSI
164 CLK_UART6_HSI
165 CLK_UART78_HSI
166 CLK_SPDIF_PLL4P
Antonio Borneo84159e82020-01-28 10:11:01 +0100[diff] [blame]167 CLK_FDCAN_PLL4R
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]168 CLK_SAI1_PLL3Q
169 CLK_SAI2_PLL3Q
170 CLK_SAI3_PLL3Q
171 CLK_SAI4_PLL3Q
172 CLK_RNG1_LSI
173 CLK_RNG2_LSI
174 CLK_LPTIM1_PCLK1
175 CLK_LPTIM23_PCLK3
176 CLK_LPTIM45_LSE
177 >;
178
Marek Vasut086fa932022-10-11 22:42:44 +0200[diff] [blame]179 /*
180 * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
181 * frac = < f >;
182 *
183 * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
184 * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
185 * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
186 * XTAL = 24 MHz
187 *
188 * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
189 * P = VCO / (P + 1)
190 * Q = VCO / (Q + 1)
191 * R = VCO / (R + 1)
192 */
193
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]194 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
195 pll2: st,pll@1 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]196 compatible = "st,stm32mp1-pll";
197 reg = <1>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]198 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
199 frac = < 0x1400 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]200 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]201 };
202
203 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
204 pll3: st,pll@2 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]205 compatible = "st,stm32mp1-pll";
206 reg = <2>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]207 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
208 frac = < 0x1a04 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]209 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]210 };
211
Marek Vasut086fa932022-10-11 22:42:44 +0200[diff] [blame]212 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]213 pll4: st,pll@3 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]214 compatible = "st,stm32mp1-pll";
215 reg = <3>;
Marek Vasutb48223e2020-08-22 22:45:25 +0200[diff] [blame]216 cfg = < 3 98 5 7 5 PQR(1,1,1) >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]217 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]218 };
219};
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]220
221&reg11 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]222 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]223};
224
225&reg18 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]226 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]227};
228
Marek Vasut5c92da92022-01-28 19:35:20 +0100[diff] [blame]229&usb33 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]230 bootph-pre-ram;
Marek Vasut5c92da92022-01-28 19:35:20 +0100[diff] [blame]231};
232
233&usbotg_hs_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]234 bootph-pre-ram;
Marek Vasut5c92da92022-01-28 19:35:20 +0100[diff] [blame]235};
236
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]237&usbotg_hs {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]238 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]239};
240
241&usbphyc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]242 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]243};
244
245&usbphyc_port0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]246 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]247};
248
249&usbphyc_port1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]250 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]251};
252
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]253&vdd_usb {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]254 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]255};