blob: 78f5ad9d602fef1fdae1a99c37d6b38c32eb28b7 [file] [log] [blame]
Pragnesh Patel8a521282020-05-29 12:14:51 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 SiFive, Inc
4 *
5 * Authors:
6 * Pragnesh Patel <pragnesh.patel@sifive.com>
7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <linux/bitops.h>
12
13/* Register offsets */
14#define L2_CACHE_CONFIG 0x000
15#define L2_CACHE_ENABLE 0x008
16
17#define MASK_NUM_WAYS GENMASK(15, 8)
18#define NUM_WAYS_SHIFT 8
19
20DECLARE_GLOBAL_DATA_PTR;
21
22int cache_enable_ways(void)
23{
24 const void *blob = gd->fdt_blob;
Heinrich Schuchardt03de50e2020-08-03 23:09:49 +020025 int node;
Pragnesh Patel8a521282020-05-29 12:14:51 +053026 fdt_addr_t base;
27 u32 config;
28 u32 ways;
29
30 volatile u32 *enable;
31
32 node = fdt_node_offset_by_compatible(blob, -1,
33 "sifive,fu540-c000-ccache");
34
35 if (node < 0)
36 return node;
37
Bin Meng54bcf262020-08-18 01:09:20 -070038 base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
39 NULL, false);
Pragnesh Patel8a521282020-05-29 12:14:51 +053040 if (base == FDT_ADDR_T_NONE)
41 return FDT_ADDR_T_NONE;
42
43 config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
44 ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
45
46 enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
47
48 /* memory barrier */
49 mb();
50 (*enable) = ways - 1;
51 /* memory barrier */
52 mb();
53 return 0;
54}