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wdenk5b845b62002-08-21 21:57:24 +00001/*
wdenk9b7f3842003-10-09 20:09:04 +00002 * (C) Copyright 2003
3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
4 *
wdenk5b845b62002-08-21 21:57:24 +00005 * (C) Copyright 2002
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk5b845b62002-08-21 21:57:24 +00009 */
10
11/*
wdenk5b845b62002-08-21 21:57:24 +000012 * Altera FPGA support
13 */
14#include <common.h>
Marek Vasutb9d4df32014-09-16 20:33:54 +020015#include <errno.h>
wdenk9b7f3842003-10-09 20:09:04 +000016#include <ACEX1K.h>
eran liberty4c373a92008-03-27 00:50:49 +010017#include <stratixII.h>
wdenk5b845b62002-08-21 21:57:24 +000018
Marek Vasut9e3a8442014-09-16 20:21:42 +020019/* Define FPGA_DEBUG to 1 to get debug printf's */
20#define FPGA_DEBUG 0
wdenk5b845b62002-08-21 21:57:24 +000021
Marek Vasutf5d25e42014-09-16 21:17:51 +020022static const struct altera_fpga {
23 enum altera_family family;
24 const char *name;
25 int (*load)(Altera_desc *, const void *, size_t);
26 int (*dump)(Altera_desc *, const void *, size_t);
27 int (*info)(Altera_desc *);
28} altera_fpga[] = {
29#if defined(CONFIG_FPGA_ACEX1K)
30 { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
31 { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
32#elif defined(CONFIG_FPGA_CYCLON2)
33 { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
34 { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
35#endif
36#if defined(CONFIG_FPGA_STRATIX_II)
37 { Altera_StratixII, "StratixII", StratixII_load,
38 StratixII_dump, StratixII_info },
39#endif
Stefan Roesed919d722016-02-12 13:48:02 +010040#if defined(CONFIG_FPGA_STRATIX_V)
41 { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
42#endif
Pavel Machekc7213802014-09-08 14:08:45 +020043#if defined(CONFIG_FPGA_SOCFPGA)
44 { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
45#endif
Marek Vasutf5d25e42014-09-16 21:17:51 +020046};
47
Marek Vasutff4072c2014-09-16 20:32:51 +020048static int altera_validate(Altera_desc *desc, const char *fn)
49{
50 if (!desc) {
51 printf("%s: NULL descriptor!\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020052 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020053 }
54
55 if ((desc->family < min_altera_type) ||
56 (desc->family > max_altera_type)) {
57 printf("%s: Invalid family type, %d\n", fn, desc->family);
Marek Vasutb9d4df32014-09-16 20:33:54 +020058 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020059 }
60
61 if ((desc->iface < min_altera_iface_type) ||
62 (desc->iface > max_altera_iface_type)) {
63 printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
Marek Vasutb9d4df32014-09-16 20:33:54 +020064 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020065 }
66
67 if (!desc->size) {
68 printf("%s: NULL part size\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020069 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020070 }
71
Marek Vasutb9d4df32014-09-16 20:33:54 +020072 return 0;
Marek Vasutff4072c2014-09-16 20:32:51 +020073}
wdenk9b7f3842003-10-09 20:09:04 +000074
Marek Vasutf5d25e42014-09-16 21:17:51 +020075static const struct altera_fpga *
76altera_desc_to_fpga(Altera_desc *desc, const char *fn)
wdenk5b845b62002-08-21 21:57:24 +000077{
Marek Vasutf5d25e42014-09-16 21:17:51 +020078 int i;
wdenk9b7f3842003-10-09 20:09:04 +000079
Marek Vasutf5d25e42014-09-16 21:17:51 +020080 if (altera_validate(desc, fn)) {
81 printf("%s: Invalid device descriptor\n", fn);
82 return NULL;
Marek Vasut18221352014-09-16 20:29:24 +020083 }
84
Marek Vasutf5d25e42014-09-16 21:17:51 +020085 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
86 if (desc->family == altera_fpga[i].family)
87 break;
88 }
wdenk9b7f3842003-10-09 20:09:04 +000089
Marek Vasutf5d25e42014-09-16 21:17:51 +020090 if (i == ARRAY_SIZE(altera_fpga)) {
91 printf("%s: Unsupported family type, %d\n", fn, desc->family);
92 return NULL;
wdenk9b7f3842003-10-09 20:09:04 +000093 }
94
Marek Vasutf5d25e42014-09-16 21:17:51 +020095 return &altera_fpga[i];
wdenk5b845b62002-08-21 21:57:24 +000096}
97
Marek Vasutf5d25e42014-09-16 21:17:51 +020098int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
wdenk5b845b62002-08-21 21:57:24 +000099{
Marek Vasutf5d25e42014-09-16 21:17:51 +0200100 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000101
Marek Vasutf5d25e42014-09-16 21:17:51 +0200102 if (!fpga)
Marek Vasut18221352014-09-16 20:29:24 +0200103 return FPGA_FAIL;
Marek Vasut18221352014-09-16 20:29:24 +0200104
Marek Vasutf5d25e42014-09-16 21:17:51 +0200105 debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
106 __func__, fpga->name);
107 if (fpga->load)
108 return fpga->load(desc, buf, bsize);
109 return 0;
110}
wdenk9b7f3842003-10-09 20:09:04 +0000111
Marek Vasutf5d25e42014-09-16 21:17:51 +0200112int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
113{
114 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000115
Marek Vasutf5d25e42014-09-16 21:17:51 +0200116 if (!fpga)
117 return FPGA_FAIL;
118
119 debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
120 __func__, fpga->name);
121 if (fpga->dump)
122 return fpga->dump(desc, buf, bsize);
123 return 0;
wdenk5b845b62002-08-21 21:57:24 +0000124}
125
Marek Vasut18221352014-09-16 20:29:24 +0200126int altera_info(Altera_desc *desc)
wdenk5b845b62002-08-21 21:57:24 +0000127{
Marek Vasutf5d25e42014-09-16 21:17:51 +0200128 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000129
Marek Vasutf5d25e42014-09-16 21:17:51 +0200130 if (!fpga)
Marek Vasut18221352014-09-16 20:29:24 +0200131 return FPGA_FAIL;
wdenk9b7f3842003-10-09 20:09:04 +0000132
Marek Vasutf5d25e42014-09-16 21:17:51 +0200133 printf("Family: \t%s\n", fpga->name);
wdenk9b7f3842003-10-09 20:09:04 +0000134
Marek Vasut18221352014-09-16 20:29:24 +0200135 printf("Interface type:\t");
136 switch (desc->iface) {
137 case passive_serial:
138 printf("Passive Serial (PS)\n");
139 break;
140 case passive_parallel_synchronous:
141 printf("Passive Parallel Synchronous (PPS)\n");
142 break;
143 case passive_parallel_asynchronous:
144 printf("Passive Parallel Asynchronous (PPA)\n");
145 break;
146 case passive_serial_asynchronous:
147 printf("Passive Serial Asynchronous (PSA)\n");
148 break;
149 case altera_jtag_mode: /* Not used */
150 printf("JTAG Mode\n");
151 break;
152 case fast_passive_parallel:
153 printf("Fast Passive Parallel (FPP)\n");
154 break;
155 case fast_passive_parallel_security:
156 printf("Fast Passive Parallel with Security (FPPS)\n");
157 break;
158 /* Add new interface types here */
159 default:
160 printf("Unsupported interface type, %d\n", desc->iface);
161 }
162
163 printf("Device Size: \t%zd bytes\n"
164 "Cookie: \t0x%x (%d)\n",
165 desc->size, desc->cookie, desc->cookie);
wdenk9b7f3842003-10-09 20:09:04 +0000166
Marek Vasut18221352014-09-16 20:29:24 +0200167 if (desc->iface_fns) {
168 printf("Device Function Table @ 0x%p\n", desc->iface_fns);
Marek Vasutf5d25e42014-09-16 21:17:51 +0200169 if (fpga->info)
170 fpga->info(desc);
wdenk9b7f3842003-10-09 20:09:04 +0000171 } else {
Marek Vasut18221352014-09-16 20:29:24 +0200172 printf("No Device Function Table.\n");
wdenk9b7f3842003-10-09 20:09:04 +0000173 }
174
Marek Vasutf5d25e42014-09-16 21:17:51 +0200175 return FPGA_SUCCESS;
wdenk9b7f3842003-10-09 20:09:04 +0000176}