blob: 8ae8d1bc9628029be34b8c64cd4beb6b6d37021f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Ley Foon Tand33c2032017-04-26 02:44:41 +08002/*
3 * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
Ley Foon Tand33c2032017-04-26 02:44:41 +08004 */
5
6#ifndef _SOCFPGA_SDRAM_ARRIA10_H_
7#define _SOCFPGA_SDRAM_ARRIA10_H_
8
9#ifndef __ASSEMBLY__
10
11struct socfpga_ecc_hmc {
12 u32 ip_rev_id;
13 u32 _pad_0x4_0x7;
14 u32 ddrioctrl;
15 u32 ddrcalstat;
16 u32 mpr_0beat1;
17 u32 mpr_1beat1;
18 u32 mpr_2beat1;
19 u32 mpr_3beat1;
20 u32 mpr_4beat1;
21 u32 mpr_5beat1;
22 u32 mpr_6beat1;
23 u32 mpr_7beat1;
24 u32 mpr_8beat1;
25 u32 mpr_0beat2;
26 u32 mpr_1beat2;
27 u32 mpr_2beat2;
28 u32 mpr_3beat2;
29 u32 mpr_4beat2;
30 u32 mpr_5beat2;
31 u32 mpr_6beat2;
32 u32 mpr_7beat2;
33 u32 mpr_8beat2;
34 u32 _pad_0x58_0x5f[2];
35 u32 auto_precharge;
36 u32 _pad_0x64_0xff[39];
37 u32 eccctrl;
38 u32 eccctrl2;
39 u32 _pad_0x108_0x10f[2];
40 u32 errinten;
41 u32 errintens;
42 u32 errintenr;
43 u32 intmode;
44 u32 intstat;
45 u32 diaginttest;
46 u32 modstat;
47 u32 derraddra;
48 u32 serraddra;
49 u32 _pad_0x134_0x137;
50 u32 autowb_corraddr;
51 u32 serrcntreg;
52 u32 autowb_drop_cntreg;
53 u32 _pad_0x144_0x147;
54 u32 ecc_reg2wreccdatabus;
55 u32 ecc_rdeccdata2regbus;
56 u32 ecc_reg2rdeccdatabus;
57 u32 _pad_0x154_0x15f[3];
58 u32 ecc_diagon;
59 u32 ecc_decstat;
60 u32 _pad_0x168_0x16f[2];
61 u32 ecc_errgenaddr_0;
62 u32 ecc_errgenaddr_1;
63 u32 ecc_errgenaddr_2;
64 u32 ecc_errgenaddr_3;
65};
66
67struct socfpga_noc_ddr_scheduler {
68 u32 ddr_t_main_scheduler_id_coreid;
69 u32 ddr_t_main_scheduler_id_revisionid;
70 u32 ddr_t_main_scheduler_ddrconf;
71 u32 ddr_t_main_scheduler_ddrtiming;
72 u32 ddr_t_main_scheduler_ddrmode;
73 u32 ddr_t_main_scheduler_readlatency;
74 u32 _pad_0x20_0x34[8];
75 u32 ddr_t_main_scheduler_activate;
76 u32 ddr_t_main_scheduler_devtodev;
77};
78
79/*
80 * OCRAM firewall
81 */
82struct socfpga_noc_fw_ocram {
83 u32 enable;
84 u32 enable_set;
85 u32 enable_clear;
86 u32 region0;
87 u32 region1;
88 u32 region2;
89 u32 region3;
90 u32 region4;
91 u32 region5;
92};
93
94/* for master such as MPU and FPGA */
95struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
96 u32 enable;
97 u32 enable_set;
98 u32 enable_clear;
99 u32 _pad_0xc_0xf;
100 u32 mpuregion0addr;
101 u32 mpuregion1addr;
102 u32 mpuregion2addr;
103 u32 mpuregion3addr;
104 u32 fpga2sdram0region0addr;
105 u32 fpga2sdram0region1addr;
106 u32 fpga2sdram0region2addr;
107 u32 fpga2sdram0region3addr;
108 u32 fpga2sdram1region0addr;
109 u32 fpga2sdram1region1addr;
110 u32 fpga2sdram1region2addr;
111 u32 fpga2sdram1region3addr;
112 u32 fpga2sdram2region0addr;
113 u32 fpga2sdram2region1addr;
114 u32 fpga2sdram2region2addr;
115 u32 fpga2sdram2region3addr;
116};
117
118/* for L3 master */
119struct socfpga_noc_fw_ddr_l3 {
120 u32 enable;
121 u32 enable_set;
122 u32 enable_clear;
123 u32 hpsregion0addr;
124 u32 hpsregion1addr;
125 u32 hpsregion2addr;
126 u32 hpsregion3addr;
127 u32 hpsregion4addr;
128 u32 hpsregion5addr;
129 u32 hpsregion6addr;
130 u32 hpsregion7addr;
131};
132
133struct socfpga_io48_mmr {
134 u32 dbgcfg0;
135 u32 dbgcfg1;
136 u32 dbgcfg2;
137 u32 dbgcfg3;
138 u32 dbgcfg4;
139 u32 dbgcfg5;
140 u32 dbgcfg6;
141 u32 reserve0;
142 u32 reserve1;
143 u32 reserve2;
144 u32 ctrlcfg0;
145 u32 ctrlcfg1;
146 u32 ctrlcfg2;
147 u32 ctrlcfg3;
148 u32 ctrlcfg4;
149 u32 ctrlcfg5;
150 u32 ctrlcfg6;
151 u32 ctrlcfg7;
152 u32 ctrlcfg8;
153 u32 ctrlcfg9;
154 u32 dramtiming0;
155 u32 dramodt0;
156 u32 dramodt1;
157 u32 sbcfg0;
158 u32 sbcfg1;
159 u32 sbcfg2;
160 u32 sbcfg3;
161 u32 sbcfg4;
162 u32 sbcfg5;
163 u32 sbcfg6;
164 u32 sbcfg7;
165 u32 caltiming0;
166 u32 caltiming1;
167 u32 caltiming2;
168 u32 caltiming3;
169 u32 caltiming4;
170 u32 caltiming5;
171 u32 caltiming6;
172 u32 caltiming7;
173 u32 caltiming8;
174 u32 caltiming9;
175 u32 caltiming10;
176 u32 dramaddrw;
177 u32 sideband0;
178 u32 sideband1;
179 u32 sideband2;
180 u32 sideband3;
181 u32 sideband4;
182 u32 sideband5;
183 u32 sideband6;
184 u32 sideband7;
185 u32 sideband8;
186 u32 sideband9;
187 u32 sideband10;
188 u32 sideband11;
189 u32 sideband12;
190 u32 sideband13;
191 u32 sideband14;
192 u32 sideband15;
193 u32 dramsts;
194 u32 dbgdone;
195 u32 dbgsignals;
196 u32 dbgreset;
197 u32 dbgmatch;
198 u32 counter0mask;
199 u32 counter1mask;
200 u32 counter0match;
201 u32 counter1match;
202 u32 niosreserve0;
203 u32 niosreserve1;
204 u32 niosreserve2;
205};
206#endif /*__ASSEMBLY__*/
207
208#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
209#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT 24
210#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
211#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_SHIFT 19
212#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
213#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_SHIFT 14
214#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
215#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT 9
216#define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
217#define IO48_MMR_CTRLCFG0_AC_POS_SHIFT 7
218#define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
219#define IO48_MMR_CTRLCFG0_DIM_TYPE_SHIFT 4
220#define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
221#define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
222
223#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM BIT(30)
224#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM BIT(29)
225#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM BIT(28)
226#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM BIT(27)
227#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_DM BIT(26)
228#define IO48_MMR_CTRLCFG1_DQSTRK_EN BIT(25)
229#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
230#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_SHIFT 19
231#define IO48_MMR_CTRLCFG1_REORDER_READ BIT(18)
232#define IO48_MMR_CTRLCFG1_DBC3_REORDER_RDATA BIT(17)
233#define IO48_MMR_CTRLCFG1_DBC2_REORDER_RDATA BIT(16)
234#define IO48_MMR_CTRLCFG1_DBC1_REORDER_RDATA BIT(15)
235#define IO48_MMR_CTRLCFG1_DBC0_REORDER_RDATA BIT(14)
236#define IO48_MMR_CTRLCFG1_CTRL_REORDER_RDATA BIT(13)
237#define IO48_MMR_CTRLCFG1_REORDER_DATA BIT(12)
238#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_ECC BIT(11)
239#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_ECC BIT(10)
240#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_ECC BIT(9)
241#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_ECC BIT(8)
242#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC BIT(7)
243#define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
244#define IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT 5
245#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK 0x0000001F
246#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT 0
247
248#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK 0x3F000000
249#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_SHIFT 24
250#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK 0x00FC0000
251#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT 18
252#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK 0x0003F000
253#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT 12
254#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK 0x00000FC0
255#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_SHIFT 6
256#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK 0x0000003F
257#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT 0
258
259#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK 0x3F000000
260#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT 24
261#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK 0x00FC0000
262#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT 18
263#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK 0x0003F000
264#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_SHIFT 12
265#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK 0x00000FC0
266#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT 6
267#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK 0x0000003F
268#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT 0
269
270#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK 0x3F000000
271#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_SHIFT 24
272#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK 0x00FC0000
273#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_SHIFT 18
274#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK 0x0003F000
275#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_SHIFT 12
276#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK 0x00000FC0
277#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT 6
278#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK 0x0000003F
279#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT 0
280
281#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK 0x3F000000
282#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_SHIFT 24
283#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK 0x00FC0000
284#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_SHIFT 18
285#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK 0x0003F000
286#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT 12
287#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK 0x00000FC0
288#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT 6
289#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK 0x0000003F
290#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT 0
291
292#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK 0xFC000000
293#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_SHIFT 26
294#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK 0x03FC0000
295#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_SHIFT 18
296#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK 0x0003F000
297#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_SHIFT 12
298#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK 0x00000FC0
299#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT 6
300#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK 0x0000003F
301#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT 0
302
303#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK 0x000000FF
304#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT 0
305
306#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK 0x00070000
307#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT 16
308#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK 0x0000C000
309#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT 14
310#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK 0x00003C00
311#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT 10
312#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK 0x000003E0
313#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT 5
314#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK 0x0000001F
315#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT 0
316
317#define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK 0x00000003
318
319#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK BIT(0)
320#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK BIT(1)
321#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK BIT(0)
322#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK BIT(1)
323#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK BIT(16)
324#define ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
325#define ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK BIT(8)
326#define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK BIT(0)
327#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK BIT(8)
328#define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK BIT(0)
329
330#define ALT_ECC_HMC_OCP_SERRCNTREG_VALUE 8
331
332#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0
333#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6
334#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12
335#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18
336#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21
337#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26
338#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31
339
340#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
341#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 1
342
343#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0
344#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 4
345#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 10
346
347#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0
348#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 2
349#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 4
350
351#define ALT_NOC_FW_DDR_END_ADDR_LSB 16
352#define ALT_NOC_FW_DDR_ADDR_MASK 0xFFFF
353#define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK BIT(0)
354#define ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK BIT(1)
355#define ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK BIT(2)
356#define ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK BIT(3)
357#define ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK BIT(4)
358#define ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK BIT(5)
359#define ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK BIT(6)
360#define ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK BIT(7)
361#define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK BIT(0)
362#define ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK BIT(1)
363#define ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK BIT(2)
364#define ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK BIT(3)
365#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK BIT(4)
366#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK BIT(5)
367#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK BIT(6)
368#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK BIT(7)
369#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK BIT(8)
370#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK BIT(9)
371#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK BIT(10)
372#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK BIT(11)
373#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK BIT(12)
374#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK BIT(13)
375#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK BIT(14)
376#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK BIT(15)
377
378#define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK 0x0000003F
379#endif /* _SOCFPGA_SDRAM_ARRIA10_H_ */