Blame - include/galileo/gt64260R.h - filogic/uboot

wdenk

012771d

2002-03-08 21:31:05 +0000

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/* gt64260R.h - GT64260 Internal registers definition file */

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/* Copyright - Galileo technology. */

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#ifndef __INCgt64260rh

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#define __INCgt64260rh

#ifndef GT64260

#define GT64260

#endif

/* CPU MASTER CONTROL REGISTER */

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#define CPU_CONFIGURATION 0x0

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#define CPU_MASTER_CONTROL 0x160

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/****************************************/

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/* Processor Address Space */

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/****************************************/

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/* Sdram's BAR'S */

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#define SCS_0_LOW_DECODE_ADDRESS 0x008

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#define SCS_0_HIGH_DECODE_ADDRESS 0x010

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#define SCS_1_LOW_DECODE_ADDRESS 0x208

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#define SCS_1_HIGH_DECODE_ADDRESS 0x210

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#define SCS_2_LOW_DECODE_ADDRESS 0x018

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#define SCS_2_HIGH_DECODE_ADDRESS 0x020

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#define SCS_3_LOW_DECODE_ADDRESS 0x218

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#define SCS_3_HIGH_DECODE_ADDRESS 0x220

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/* Devices BAR'S */

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#define CS_0_LOW_DECODE_ADDRESS 0x028

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#define CS_0_HIGH_DECODE_ADDRESS 0x030

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#define CS_1_LOW_DECODE_ADDRESS 0x228

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#define CS_1_HIGH_DECODE_ADDRESS 0x230

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#define CS_2_LOW_DECODE_ADDRESS 0x248

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#define CS_2_HIGH_DECODE_ADDRESS 0x250

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#define CS_3_LOW_DECODE_ADDRESS 0x038

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#define CS_3_HIGH_DECODE_ADDRESS 0x040

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#define BOOTCS_LOW_DECODE_ADDRESS 0x238

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#define BOOTCS_HIGH_DECODE_ADDRESS 0x240

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#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048

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#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050

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#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058

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#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060

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#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080

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#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088

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#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258

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#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260

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#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280

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#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288

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#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090

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#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098

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#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0

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#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8

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#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0

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#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8

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#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0

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#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8

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#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0

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#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8

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#define INTERNAL_SPACE_DECODE 0x068

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#define CPU_0_LOW_DECODE_ADDRESS 0x290

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#define CPU_0_HIGH_DECODE_ADDRESS 0x298

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#define CPU_1_LOW_DECODE_ADDRESS 0x2c0

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#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8

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#define PCI_0I_O_ADDRESS_REMAP 0x0f0

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#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8

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#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320

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#define PCI_0MEMORY1_ADDRESS_REMAP 0x100

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#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328

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#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8

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#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330

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#define PCI_0MEMORY3_ADDRESS_REMAP 0x300

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#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338

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#define PCI_1I_O_ADDRESS_REMAP 0x108

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#define PCI_1MEMORY0_ADDRESS_REMAP 0x110

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#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340

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#define PCI_1MEMORY1_ADDRESS_REMAP 0x118

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#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348

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#define PCI_1MEMORY2_ADDRESS_REMAP 0x310

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#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350

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#define PCI_1MEMORY3_ADDRESS_REMAP 0x318

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#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358

/****************************************/

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/* CPU Sync Barrier */

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/****************************************/

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#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0

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#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8

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/****************************************/

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/* CPU Access Protect */

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/****************************************/

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#define CPU_LOW_PROTECT_ADDRESS_0 0x180

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#define CPU_HIGH_PROTECT_ADDRESS_0 0x188

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#define CPU_LOW_PROTECT_ADDRESS_1 0x190

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#define CPU_HIGH_PROTECT_ADDRESS_1 0x198

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#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0

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#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8

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#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0

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#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8

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#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0

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#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8

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#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0

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#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8

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#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0

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#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8

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#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0

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#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8

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/****************************************/

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/* Snoop Control */

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/****************************************/

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#define SNOOP_BASE_ADDRESS_0 0x380

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#define SNOOP_TOP_ADDRESS_0 0x388

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#define SNOOP_BASE_ADDRESS_1 0x390

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#define SNOOP_TOP_ADDRESS_1 0x398

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#define SNOOP_BASE_ADDRESS_2 0x3a0

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#define SNOOP_TOP_ADDRESS_2 0x3a8

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#define SNOOP_BASE_ADDRESS_3 0x3b0

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#define SNOOP_TOP_ADDRESS_3 0x3b8

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/****************************************/

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/* CPU Error Report */

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/****************************************/

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#define CPU_ERROR_ADDRESS_LOW 0x070

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#define CPU_ERROR_ADDRESS_HIGH 0x078

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#define CPU_ERROR_DATA_LOW 0x128

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#define CPU_ERROR_DATA_HIGH 0x130

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#define CPU_ERROR_PARITY 0x138

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#define CPU_ERROR_CAUSE 0x140

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#define CPU_ERROR_MASK 0x148

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/****************************************/

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/* Pslave Debug */

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/****************************************/

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#define X_0_ADDRESS 0x360

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#define X_0_COMMAND_ID 0x368

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#define X_1_ADDRESS 0x370

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#define X_1_COMMAND_ID 0x378

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#define WRITE_DATA_LOW 0x3c0

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#define WRITE_DATA_HIGH 0x3c8

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#define WRITE_BYTE_ENABLE 0x3e0

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#define READ_DATA_LOW 0x3d0

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#define READ_DATA_HIGH 0x3d8

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#define READ_ID 0x3e8

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/****************************************/

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/* SDRAM and Device Address Space */

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/****************************************/

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/****************************************/

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/* SDRAM Configuration */

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/****************************************/

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#define SDRAM_CONFIGURATION 0x448

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#define SDRAM_OPERATION_MODE 0x474

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#define SDRAM_ADDRESS_DECODE 0x47c

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#define SDRAM_UMA_CONTROL 0x4a4

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#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8

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#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac

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#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0

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#define SDRAM_TIMING 0x4b4

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/****************************************/

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/* SDRAM Parameters */

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/****************************************/

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#define SDRAM_BANK0PARAMETERS 0x44C

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#define SDRAM_BANK1PARAMETERS 0x450

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#define SDRAM_BANK2PARAMETERS 0x454

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#define SDRAM_BANK3PARAMETERS 0x458

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/****************************************/

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/* SDRAM Error Report */

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/****************************************/

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#define SDRAM_ERROR_DATA_LOW 0x484

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#define SDRAM_ERROR_DATA_HIGH 0x480

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#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490

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#define SDRAM_RECEIVED_ECC 0x488

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#define SDRAM_CALCULATED_ECC 0x48c

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#define SDRAM_ECC_CONTROL 0x494

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#define SDRAM_ECC_ERROR_COUNTER 0x498

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/****************************************/

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/* SDunit Debug (for internal use) */

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/****************************************/

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#define X0_ADDRESS 0x500

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#define X0_COMMAND_AND_ID 0x504

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#define X0_WRITE_DATA_LOW 0x508

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#define X0_WRITE_DATA_HIGH 0x50c

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#define X0_WRITE_BYTE_ENABLE 0x518

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#define X0_READ_DATA_LOW 0x510

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#define X0_READ_DATA_HIGH 0x514

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#define X0_READ_ID 0x51c

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#define X1_ADDRESS 0x520

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#define X1_COMMAND_AND_ID 0x524

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#define X1_WRITE_DATA_LOW 0x528

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#define X1_WRITE_DATA_HIGH 0x52c

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#define X1_WRITE_BYTE_ENABLE 0x538

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#define X1_READ_DATA_LOW 0x530

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#define X1_READ_DATA_HIGH 0x534

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#define X1_READ_ID 0x53c

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#define X0_SNOOP_ADDRESS 0x540

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#define X0_SNOOP_COMMAND 0x544

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#define X1_SNOOP_ADDRESS 0x548

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#define X1_SNOOP_COMMAND 0x54c

/****************************************/

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/* Device Parameters */

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/****************************************/

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#define DEVICE_BANK0PARAMETERS 0x45c

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#define DEVICE_BANK1PARAMETERS 0x460

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#define DEVICE_BANK2PARAMETERS 0x464

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#define DEVICE_BANK3PARAMETERS 0x468

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#define DEVICE_BOOT_BANK_PARAMETERS 0x46c

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#define DEVICE_CONTROL 0x4c0

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#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8

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#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc

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#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4

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/****************************************/

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/* Device Interrupt */

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/****************************************/

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#define DEVICE_INTERRUPT_CAUSE 0x4d0

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#define DEVICE_INTERRUPT_MASK 0x4d4

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#define DEVICE_ERROR_ADDRESS 0x4d8

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/****************************************/

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/* DMA Record */

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/****************************************/

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#define CHANNEL0_DMA_BYTE_COUNT 0x800

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#define CHANNEL1_DMA_BYTE_COUNT 0x804

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#define CHANNEL2_DMA_BYTE_COUNT 0x808

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#define CHANNEL3_DMA_BYTE_COUNT 0x80C

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#define CHANNEL4_DMA_BYTE_COUNT 0x900

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#define CHANNEL5_DMA_BYTE_COUNT 0x904

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#define CHANNEL6_DMA_BYTE_COUNT 0x908

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#define CHANNEL7_DMA_BYTE_COUNT 0x90C

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#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810

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#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814

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#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818

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#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C

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#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910

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#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914

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#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918

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#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C

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#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820

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#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824

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#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828

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#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C

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#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920

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#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924

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#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928

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#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C

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#define CHANNEL0NEXT_RECORD_POINTER 0x830

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#define CHANNEL1NEXT_RECORD_POINTER 0x834

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#define CHANNEL2NEXT_RECORD_POINTER 0x838

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#define CHANNEL3NEXT_RECORD_POINTER 0x83C

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#define CHANNEL4NEXT_RECORD_POINTER 0x930

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#define CHANNEL5NEXT_RECORD_POINTER 0x934

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#define CHANNEL6NEXT_RECORD_POINTER 0x938

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#define CHANNEL7NEXT_RECORD_POINTER 0x93C

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#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870

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#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874

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#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878

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#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C

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#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970

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#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974

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#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978

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#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C

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#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890

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#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894

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#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898

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#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c

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#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990

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#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994

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#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998

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#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c

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#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0

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#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4

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#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8

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#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac

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#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0

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#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4

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#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8

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#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac

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#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0

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#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4

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#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8

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#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc

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#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0

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#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4

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#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8

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#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc

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/****************************************/

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/* DMA Channel Control */

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/****************************************/

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#define CHANNEL0CONTROL 0x840

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#define CHANNEL0CONTROL_HIGH 0x880

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#define CHANNEL1CONTROL 0x844

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#define CHANNEL1CONTROL_HIGH 0x884

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#define CHANNEL2CONTROL 0x848

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#define CHANNEL2CONTROL_HIGH 0x888

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#define CHANNEL3CONTROL 0x84C

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#define CHANNEL3CONTROL_HIGH 0x88C

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#define CHANNEL4CONTROL 0x940

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#define CHANNEL4CONTROL_HIGH 0x980

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#define CHANNEL5CONTROL 0x944

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#define CHANNEL5CONTROL_HIGH 0x984

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#define CHANNEL6CONTROL 0x948

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#define CHANNEL6CONTROL_HIGH 0x988

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#define CHANNEL7CONTROL 0x94C

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#define CHANNEL7CONTROL_HIGH 0x98C

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/****************************************/

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/* DMA Arbiter */

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/****************************************/

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#define ARBITER_CONTROL_0_3 0x860

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#define ARBITER_CONTROL_4_7 0x960

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/****************************************/

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/* DMA Interrupt */

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/****************************************/

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#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0

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#define CHANELS0_3_INTERRUPT_MASK 0x8c4

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#define CHANELS0_3_ERROR_ADDRESS 0x8c8

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#define CHANELS0_3_ERROR_SELECT 0x8cc

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#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0

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#define CHANELS4_7_INTERRUPT_MASK 0x9c4

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#define CHANELS4_7_ERROR_ADDRESS 0x9c8

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#define CHANELS4_7_ERROR_SELECT 0x9cc

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/****************************************/

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/* DMA Debug (for internal use) */

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/****************************************/

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#define DMA_X0_ADDRESS 0x8e0

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#define DMA_X0_COMMAND_AND_ID 0x8e4

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#define DMA_X0_WRITE_DATA_LOW 0x8e8

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#define DMA_X0_WRITE_DATA_HIGH 0x8ec

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#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8

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#define DMA_X0_READ_DATA_LOW 0x8f0

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#define DMA_X0_READ_DATA_HIGH 0x8f4

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#define DMA_X0_READ_ID 0x8fc

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#define DMA_X1_ADDRESS 0x9e0

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#define DMA_X1_COMMAND_AND_ID 0x9e4

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#define DMA_X1_WRITE_DATA_LOW 0x9e8

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#define DMA_X1_WRITE_DATA_HIGH 0x9ec

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#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8

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#define DMA_X1_READ_DATA_LOW 0x9f0

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#define DMA_X1_READ_DATA_HIGH 0x9f4

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#define DMA_X1_READ_ID 0x9fc

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/****************************************/

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/* Timer_Counter */

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/****************************************/

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#define TIMER_COUNTER0 0x850

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#define TIMER_COUNTER1 0x854

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#define TIMER_COUNTER2 0x858

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#define TIMER_COUNTER3 0x85C

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#define TIMER_COUNTER_0_3_CONTROL 0x864

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#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868

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#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c

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#define TIMER_COUNTER4 0x950

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#define TIMER_COUNTER5 0x954

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#define TIMER_COUNTER6 0x958

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#define TIMER_COUNTER7 0x95C

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#define TIMER_COUNTER_4_7_CONTROL 0x964

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#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968

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#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c

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/****************************************/

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/* PCI Slave Address Decoding */

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/****************************************/

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#define PCI_0SCS_0_BANK_SIZE 0xc08

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#define PCI_1SCS_0_BANK_SIZE 0xc88

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#define PCI_0SCS_1_BANK_SIZE 0xd08

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#define PCI_1SCS_1_BANK_SIZE 0xd88

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#define PCI_0SCS_2_BANK_SIZE 0xc0c

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#define PCI_1SCS_2_BANK_SIZE 0xc8c

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#define PCI_0SCS_3_BANK_SIZE 0xd0c

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#define PCI_1SCS_3_BANK_SIZE 0xd8c

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#define PCI_0CS_0_BANK_SIZE 0xc10

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#define PCI_1CS_0_BANK_SIZE 0xc90

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#define PCI_0CS_1_BANK_SIZE 0xd10

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#define PCI_1CS_1_BANK_SIZE 0xd90

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#define PCI_0CS_2_BANK_SIZE 0xd18

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#define PCI_1CS_2_BANK_SIZE 0xd98

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#define PCI_0CS_3_BANK_SIZE 0xc14

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#define PCI_1CS_3_BANK_SIZE 0xc94

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#define PCI_0CS_BOOT_BANK_SIZE 0xd14

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#define PCI_1CS_BOOT_BANK_SIZE 0xd94

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#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c

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#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c

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#define PCI_0P2P_MEM1_BAR_SIZE 0xd20

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#define PCI_1P2P_MEM1_BAR_SIZE 0xda0

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#define PCI_0P2P_I_O_BAR_SIZE 0xd24

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#define PCI_1P2P_I_O_BAR_SIZE 0xda4

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#define PCI_0CPU_BAR_SIZE 0xd28

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#define PCI_1CPU_BAR_SIZE 0xda8

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#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00

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#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80

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#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04

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#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84

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#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08

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#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88

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#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c

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#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c

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#define PCI_0DAC_CS_0_BANK_SIZE 0xe10

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#define PCI_1DAC_CS_0_BANK_SIZE 0xe90

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#define PCI_0DAC_CS_1_BANK_SIZE 0xe14

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#define PCI_1DAC_CS_1_BANK_SIZE 0xe94

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#define PCI_0DAC_CS_2_BANK_SIZE 0xe18

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#define PCI_1DAC_CS_2_BANK_SIZE 0xe98

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#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c

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#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c

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#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20

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#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0

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#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24

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#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4

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#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28

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#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8

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#define PCI_0DAC_CPU_BAR_SIZE 0xe2c

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#define PCI_1DAC_CPU_BAR_SIZE 0xeac

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#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c

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#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac

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#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c

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#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc

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#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48

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#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8

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#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48

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#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8

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#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c

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#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc

476

#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c

477

#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc

478

#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50

479

#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0

480

#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50

481

#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0

482

#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58

483

#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8

484

#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54

485

#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4

486

#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54

487

#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4

488

#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c

489

#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc

490

#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60

491

#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0

492

#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64

493

#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4

494

#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68

495

#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8

496

#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c

497

#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec

498

#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70

499

#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0

500

#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00

501

#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0

502

#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04

503

#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84

504

#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08

505

#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88

506

#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c

507

#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c

508

#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10

509

#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90

510

#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14

511

#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94

512

#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18

513

#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98

514

#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c

515

#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c

516

#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20

517

#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0

518

#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24

519

#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4

520

#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28

521

#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8

522

#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c

523

#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac

524

#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30

525

#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0

526

#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34

527

#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4

528

#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38

529

#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8

530

#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c

531

#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc

532

533

/****************************************/

534

/* PCI Control */

535

/****************************************/

536

537

#define PCI_0COMMAND 0xc00

538

#define PCI_1COMMAND 0xc80

539

#define PCI_0MODE 0xd00

540

#define PCI_1MODE 0xd80

541

#define PCI_0TIMEOUT_RETRY 0xc04

542

#define PCI_1TIMEOUT_RETRY 0xc84

543

#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04

544

#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84

545

#define MSI_0TRIGGER_TIMER 0xc38

546

#define MSI_1TRIGGER_TIMER 0xcb8

547

#define PCI_0ARBITER_CONTROL 0x1d00

548

#define PCI_1ARBITER_CONTROL 0x1d80

549

/* changing untill here */

550

#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08

551

#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c

552

#define PCI_0CROSS_BAR_TIMEOUT 0x1d04

553

#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18

554

#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c

555

#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10

556

#define PCI_0P2P_CONFIGURATION 0x1d14

557

#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00

558

#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04

559

#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08

560

#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10

561

#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14

562

#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18

563

#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20

564

#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24

565

#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28

566

#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30

567

#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34

568

#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38

569

#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40

570

#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44

571

#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48

572

#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50

573

#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54

574

#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58

575

#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60

576

#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64

577

#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68

578

#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70

579

#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74

580

#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78

581

#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88

582

#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c

583

#define PCI_1CROSS_BAR_TIMEOUT 0x1d84

584

#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98

585

#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c

586

#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90

587

#define PCI_1P2P_CONFIGURATION 0x1d94

588

#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80

589

#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84

590

#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88

591

#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90

592

#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94

593

#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98

594

#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0

595

#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4

596

#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8

597

#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0

598

#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4

599

#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8

600

#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0

601

#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4

602

#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8

603

#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0

604

#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4

605

#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8

606

#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0

607

#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4

608

#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8

609

#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0

610

#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4

611

#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8

612

613

/****************************************/

614

/* PCI Snoop Control */

615

/****************************************/

616

617

#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00

618

#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04

619

#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08

620

#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10

621

#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14

622

#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18

623

#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20

624

#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24

625

#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28

626

#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30

627

#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34

628

#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38

629

#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80

630

#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84

631

#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88

632

#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90

633

#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94

634

#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98

635

#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0

636

#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4

637

#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8

638

#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0

639

#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4

640

#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8

641

642

/****************************************/

643

/* PCI Configuration Address */

644

/****************************************/

645

646

#define PCI_0CONFIGURATION_ADDRESS 0xcf8

647

#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc

648

#define PCI_1CONFIGURATION_ADDRESS 0xc78

649

#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c

650

#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34

651

#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4

652

653

/****************************************/

654

/* PCI Error Report */

655

/****************************************/

656

657

#define PCI_0SERR_MASK 0xc28

658

#define PCI_0ERROR_ADDRESS_LOW 0x1d40

659

#define PCI_0ERROR_ADDRESS_HIGH 0x1d44

660

#define PCI_0ERROR_DATA_LOW 0x1d48

661

#define PCI_0ERROR_DATA_HIGH 0x1d4c

662

#define PCI_0ERROR_COMMAND 0x1d50

663

#define PCI_0ERROR_CAUSE 0x1d58

664

#define PCI_0ERROR_MASK 0x1d5c

665

#define PCI_1SERR_MASK 0xca8

666

#define PCI_1ERROR_ADDRESS_LOW 0x1dc0

667

#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4

668

#define PCI_1ERROR_DATA_LOW 0x1dc8

669

#define PCI_1ERROR_DATA_HIGH 0x1dcc

670

#define PCI_1ERROR_COMMAND 0x1dd0

671

#define PCI_1ERROR_CAUSE 0x1dd8

672

#define PCI_1ERROR_MASK 0x1ddc

673

674

675

/****************************************/

676

/* Lslave Debug (for internal use) */

677

/****************************************/

678

679

#define L_SLAVE_X0_ADDRESS 0x1d20

680

#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24

681

#define L_SLAVE_X1_ADDRESS 0x1d28

682

#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c

683

#define L_SLAVE_WRITE_DATA_LOW 0x1d30

684

#define L_SLAVE_WRITE_DATA_HIGH 0x1d34

685

#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60

686

#define L_SLAVE_READ_DATA_LOW 0x1d38

687

#define L_SLAVE_READ_DATA_HIGH 0x1d3c

688

#define L_SLAVE_READ_ID 0x1d64

689

690

/****************************************/

691

/* PCI Configuration Function 0 */

692

/****************************************/

693

694

#define PCI_DEVICE_AND_VENDOR_ID 0x000

695

#define PCI_STATUS_AND_COMMAND 0x004

696

#define PCI_CLASS_CODE_AND_REVISION_ID 0x008

697

#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C

698

#define PCI_SCS_0_BASE_ADDRESS 0x010

699

#define PCI_SCS_1_BASE_ADDRESS 0x014

700

#define PCI_SCS_2_BASE_ADDRESS 0x018

701

#define PCI_SCS_3_BASE_ADDRESS 0x01C

702

#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020

703

#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024

704

#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C

705

#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030

706

#define PCI_CAPABILTY_LIST_POINTER 0x034

707

#define PCI_INTERRUPT_PIN_AND_LINE 0x03C

708

#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040

709

#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044

710

#define PCI_VPD_ADDRESS 0x048

711

#define PCI_VPD_DATA 0x04c

712

#define PCI_MSI_MESSAGE_CONTROL 0x050

713

#define PCI_MSI_MESSAGE_ADDRESS 0x054

714

#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058

715

#define PCI_MSI_MESSAGE_DATA 0x05c

716

#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058

717

718

/****************************************/

719

/* PCI Configuration Function 1 */

720

/****************************************/

721

722

#define PCI_CS_0_BASE_ADDRESS 0x110

723

#define PCI_CS_1_BASE_ADDRESS 0x114

724

#define PCI_CS_2_BASE_ADDRESS 0x118

725

#define PCI_CS_3_BASE_ADDRESS 0x11c

726

#define PCI_BOOTCS_BASE_ADDRESS 0x120

727

728

/****************************************/

729

/* PCI Configuration Function 2 */

730

/****************************************/

731

732

#define PCI_P2P_MEM0_BASE_ADDRESS 0x210

733

#define PCI_P2P_MEM1_BASE_ADDRESS 0x214

734

#define PCI_P2P_I_O_BASE_ADDRESS 0x218

735

#define PCI_CPU_BASE_ADDRESS 0x21c

736

737

/****************************************/

738

/* PCI Configuration Function 4 */

739

/****************************************/

740

741

#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410

742

#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414

743

#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418

744

#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c

745

#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420

746

#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424

747

748

749

/****************************************/

750

/* PCI Configuration Function 5 */

751

/****************************************/

752

753

#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510

754

#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514

755

#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518

756

#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c

757

#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520

758

#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524

759

760

761

/****************************************/

762

/* PCI Configuration Function 6 */

763

/****************************************/

764

765

#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610

766

#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614

767

#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618

768

#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c

769

#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620

770

#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624

771

772

/****************************************/

773

/* PCI Configuration Function 7 */

774

/****************************************/

775

776

#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710

777

#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714

778

#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718

779

#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c

780

#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720

781

#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724

782

783

/****************************************/

784

/* Interrupts */

785

/****************************************/

786

787

#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18

788

#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68

789

#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c

790

#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c

791

#define CPU_SELECT_CAUSE_REGISTER 0xc70

792

#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24

793

#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64

794

#define PCI_0SELECT_CAUSE 0xc74

795

#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4

796

#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4

797

#define PCI_1SELECT_CAUSE 0xcf4

798

#define CPU_INT_0_MASK 0xe60

799

#define CPU_INT_1_MASK 0xe64

800

#define CPU_INT_2_MASK 0xe68

801

#define CPU_INT_3_MASK 0xe6c

802

803

/****************************************/

804

/* I20 Support registers */

805

/****************************************/

806

807

#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010

808

#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014

809

#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018

810

#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C

811

#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020

812

#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024

813

#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028

814

#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C

815

#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030

816

#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034

817

#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040

818

#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044

819

#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050

820

#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054

821

#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060

822

#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064

823

#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068

824

#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C

825

#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070

826

#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074

827

#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078

828

#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C

829

830

#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10

831

#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14

832

#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18

833

#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C

834

#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20

835

#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24

836

#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28

837

#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C

838

#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30

839

#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34

840

#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40

841

#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44

842

#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50

843

#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54

844

#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60

845

#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64

846

#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68

847

#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C

848

#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70

849

#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74

850

#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78

851

#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C

852

853

/****************************************/

854

/* Communication Unit Registers */

855

/****************************************/

856

857

#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200

858

#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204

859

#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208

860

#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c

861

#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210

862

#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214

863

#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218

864

#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220

865

#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224

866

#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228

867

#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c

868

#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230

869

#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234

870

#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238

871

#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240

872

#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244

873

#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248

874

#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c

875

#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250

876

#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254

877

#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258

878

#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280

879

#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284

880

#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288

881

#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c

882

#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290

883

#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294

884

#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0

885

#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4

886

#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8

887

#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc

888

#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0

889

#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4

890

#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320

891

#define SERIAL_INIT_LAST_DATA 0xf324

892

#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328

893

#define COMM_UNIT_ARBITER_CONTROL 0xf300

894

#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304

895

#define COMM_UNIT_INTERRUPT_CAUSE 0xf310

896

#define COMM_UNIT_INTERRUPT_MASK 0xf314

897

#define COMM_UNIT_ERROR_ADDRESS 0xf314

898

899

/****************************************/

900

/* Cunit Debug (for internal use) */

901

/****************************************/

902

903

#define CUNIT_ADDRESS 0xf340

904

#define CUNIT_COMMAND_AND_ID 0xf344

905

#define CUNIT_WRITE_DATA_LOW 0xf348

906

#define CUNIT_WRITE_DATA_HIGH 0xf34c

907

#define CUNIT_WRITE_BYTE_ENABLE 0xf358

908

#define CUNIT_READ_DATA_LOW 0xf350

909

#define CUNIT_READ_DATA_HIGH 0xf354

910

#define CUNIT_READ_ID 0xf35c

911

912

/****************************************/

913

/* Fast Ethernet Unit Registers */

914

/****************************************/

/* Ethernet */

#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000

919

#define ETHERNET_SMI_REGISTER 0x2010

/* Ethernet 0 */

#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400

924

#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408

925

#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410

926

#define ETHERNET0_PORT_STATUS_REGISTER 0x2418

927

#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420

928

#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428

929

#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430

930

#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438

931

#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440

932

#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448

933

#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450

934

#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458

935

#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480

936

#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484

937

#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488

938

#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c

939

#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0

940

#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4

941

#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8

942

#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac

943

#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0

944

#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4

945

#define ETHERNET0_MIB_COUNTER_BASE 0x2500

/* Ethernet 1 */

#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800

950

#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808

951

#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810

952

#define ETHERNET1_PORT_STATUS_REGISTER 0x2818

953

#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820

954

#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828

955

#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830

956

#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838

957

#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840

958

#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848

959

#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850

960

#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858

961

#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880

962

#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884

963

#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888

964

#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c

965

#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0

966

#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4

967

#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8

968

#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac

969

#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0

970

#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4

971

#define ETHERNET1_MIB_COUNTER_BASE 0x2900

/* Ethernet 2 */

#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00

976

#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08

977

#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10

978

#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18

979

#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20

980

#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28

981

#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30

982

#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38

983

#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40

984

#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48

985

#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50

986

#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58

987

#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80

988

#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84

989

#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88

990

#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c

991

#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0

992

#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4

993

#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8

994

#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac

995

#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0

996

#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4

997

#define ETHERNET2_MIB_COUNTER_BASE 0x2d00

998

999

/****************************************/

1000

/* SDMA Registers */

1001

/****************************************/

1002

1003

#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0

1004

#define CHANNEL0_CONFIGURATION_REGISTER 0x4000

1005

#define CHANNEL0_COMMAND_REGISTER 0x4008

1006

#define CHANNEL0_RX_CMD_STATUS 0x4800

1007

#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804

1008

#define CHANNEL0_RX_BUFFER_POINTER 0x4808

1009

#define CHANNEL0_RX_NEXT_POINTER 0x480c

1010

#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810

1011

#define CHANNEL0_TX_CMD_STATUS 0x4C00

1012

#define CHANNEL0_TX_PACKET_SIZE 0x4C04

1013

#define CHANNEL0_TX_BUFFER_POINTER 0x4C08

1014

#define CHANNEL0_TX_NEXT_POINTER 0x4C0c

1015

#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10

1016

#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14

1017

#define CHANNEL1_CONFIGURATION_REGISTER 0x5000

1018

#define CHANNEL1_COMMAND_REGISTER 0x5008

1019

#define CHANNEL1_RX_CMD_STATUS 0x5800

1020

#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804

1021

#define CHANNEL1_RX_BUFFER_POINTER 0x5808

1022

#define CHANNEL1_RX_NEXT_POINTER 0x580c

1023

#define CHANNEL1_TX_CMD_STATUS 0x5C00

1024

#define CHANNEL1_TX_PACKET_SIZE 0x5C04

1025

#define CHANNEL1_TX_BUFFER_POINTER 0x5C08

1026

#define CHANNEL1_TX_NEXT_POINTER 0x5C0c

1027

#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810

1028

#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10

1029

#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14

1030

#define CHANNEL2_CONFIGURATION_REGISTER 0x6000

1031

#define CHANNEL2_COMMAND_REGISTER 0x6008

1032

#define CHANNEL2_RX_CMD_STATUS 0x6800

1033

#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804

1034

#define CHANNEL2_RX_BUFFER_POINTER 0x6808

1035

#define CHANNEL2_RX_NEXT_POINTER 0x680c

1036

#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810

1037

#define CHANNEL2_TX_CMD_STATUS 0x6C00

1038

#define CHANNEL2_TX_PACKET_SIZE 0x6C04

1039

#define CHANNEL2_TX_BUFFER_POINTER 0x6C08

1040

#define CHANNEL2_TX_NEXT_POINTER 0x6C0c

1041

#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810

1042

#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10

1043

#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14

/* SDMA Interrupt */

#define SDMA_CAUSE 0xb820

1048

#define SDMA_MASK 0xb8a0

1049

1050

1051

/****************************************/

1052

/* Baude Rate Generators Registers */

1053

/****************************************/

/* BRG 0 */

#define BRG0_CONFIGURATION_REGISTER 0xb200

1058

#define BRG0_BAUDE_TUNING_REGISTER 0xb204

/* BRG 1 */

#define BRG1_CONFIGURATION_REGISTER 0xb208

1063

#define BRG1_BAUDE_TUNING_REGISTER 0xb20c

/* BRG 2 */

#define BRG2_CONFIGURATION_REGISTER 0xb210

1068

#define BRG2_BAUDE_TUNING_REGISTER 0xb214

/* BRG Interrupts */

#define BRG_CAUSE_REGISTER 0xb834

1073

#define BRG_MASK_REGISTER 0xb8b4

/* MISC */

#define MAIN_ROUTING_REGISTER 0xb400

1078

#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404

1079

#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408

1080

#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c

1081

#define WATCHDOG_CONFIGURATION_REGISTER 0xb410

1082

#define WATCHDOG_VALUE_REGISTER 0xb414

1083

1084

1085

/****************************************/

1086

/* Flex TDM Registers */

1087

/****************************************/

/* FTDM Port */

#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800

1092

#define FLEXTDM_RECEIVE_READ_POINTER 0xa804

1093

#define FLEXTDM_CONFIGURATION_REGISTER 0xa808

1094

#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c

1095

#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810

1096

#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814

1097

#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818

1098

1099

/* FTDM Interrupts */

1100

1101

#define FTDM_CAUSE_REGISTER 0xb830

1102

#define FTDM_MASK_REGISTER 0xb8b0

1103

1104

1105

/****************************************/

1106

/* GPP Interface Registers */

1107

/****************************************/

1108

1109

#define GPP_IO_CONTROL 0xf100

1110

#define GPP_LEVEL_CONTROL 0xf110

1111

#define GPP_VALUE 0xf104

1112

#define GPP_INTERRUPT_CAUSE 0xf108

1113

#define GPP_INTERRUPT_MASK 0xf10c

1114

1115

#define MPP_CONTROL0 0xf000

1116

#define MPP_CONTROL1 0xf004

1117

#define MPP_CONTROL2 0xf008

1118

#define MPP_CONTROL3 0xf00c

1119

#define DEBUG_PORT_MULTIPLEX 0xf014

1120

#define SERIAL_PORT_MULTIPLEX 0xf010

1121

1122

/****************************************/

1123

/* I2C Registers */

1124

/****************************************/

1125

1126

#define I2C_SLAVE_ADDRESS 0xc000

1127

#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040

1128

#define I2C_DATA 0xc004

1129

#define I2C_CONTROL 0xc008

1130

#define I2C_STATUS_BAUDE_RATE 0xc00C

1131

#define I2C_SOFT_RESET 0xc01c

1132

1133

/****************************************/

1134

/* MPSC Registers */

1135

/****************************************/

/* MPSC0 */

#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000

1140

#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004

1141

#define MPSC0_PROTOCOL_CONFIGURATION 0x8008

1142

#define CHANNEL0_REGISTER1 0x800c

1143

#define CHANNEL0_REGISTER2 0x8010

1144

#define CHANNEL0_REGISTER3 0x8014

1145

#define CHANNEL0_REGISTER4 0x8018

1146

#define CHANNEL0_REGISTER5 0x801c

1147

#define CHANNEL0_REGISTER6 0x8020

1148

#define CHANNEL0_REGISTER7 0x8024

1149

#define CHANNEL0_REGISTER8 0x8028

1150

#define CHANNEL0_REGISTER9 0x802c

1151

#define CHANNEL0_REGISTER10 0x8030

1152

#define CHANNEL0_REGISTER11 0x8034

/* MPSC1 */

#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840

1157

#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844

1158

#define MPSC1_PROTOCOL_CONFIGURATION 0x8848

1159

#define CHANNEL1_REGISTER1 0x884c

1160

#define CHANNEL1_REGISTER2 0x8850

1161

#define CHANNEL1_REGISTER3 0x8854

1162

#define CHANNEL1_REGISTER4 0x8858

1163

#define CHANNEL1_REGISTER5 0x885c

1164

#define CHANNEL1_REGISTER6 0x8860

1165

#define CHANNEL1_REGISTER7 0x8864

1166

#define CHANNEL1_REGISTER8 0x8868

1167

#define CHANNEL1_REGISTER9 0x886c

1168

#define CHANNEL1_REGISTER10 0x8870

1169

#define CHANNEL1_REGISTER11 0x8874

/* MPSC2 */

#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040

1174

#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044

1175

#define MPSC2_PROTOCOL_CONFIGURATION 0x9048

1176

#define CHANNEL2_REGISTER1 0x904c

1177

#define CHANNEL2_REGISTER2 0x9050

1178

#define CHANNEL2_REGISTER3 0x9054

1179

#define CHANNEL2_REGISTER4 0x9058

1180

#define CHANNEL2_REGISTER5 0x905c

1181

#define CHANNEL2_REGISTER6 0x9060

1182

#define CHANNEL2_REGISTER7 0x9064

1183

#define CHANNEL2_REGISTER8 0x9068

1184

#define CHANNEL2_REGISTER9 0x906c

1185

#define CHANNEL2_REGISTER10 0x9070

1186

#define CHANNEL2_REGISTER11 0x9074

1187

1188

/* MPSCs Interupts */

1189

1190

#define MPSC0_CAUSE 0xb824

1191

#define MPSC0_MASK 0xb8a4

1192

#define MPSC1_CAUSE 0xb828

1193

#define MPSC1_MASK 0xb8a8

1194

#define MPSC2_CAUSE 0xb82c

1195

#define MPSC2_MASK 0xb8ac

1196

1197

#endif /* __INCgt64260rh */