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git01.mediatek.com / filogic / uboot / 01250d8654143102252eeb77b9ac310c9c0930fc / . / arch / arm / dts / k3-j721e-mcu-wakeup.dtsi
blob: 70d5bcaa7298100773b18a2a65a32eafe187f310 [file] [log] [blame]
Lokesh Vutla5839b1c2019-06-13 10:29:53 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
4 *
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8&cbass_mcu_wakeup {
9 dmsc: dmsc@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
12
13 mbox-names = "rx", "tx";
14
15 mboxes= <&secure_proxy_main 11>,
16 <&secure_proxy_main 13>;
17
18 reg-names = "debug_messages";
19 reg = <0x00 0x44083000 0x0 0x1000>;
20
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
24 };
25
26 k3_clks: clocks {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
29 ti,scan-clocks-from-dt;
30 };
31
32 k3_reset: reset-controller {
33 compatible = "ti,sci-reset";
34 #reset-cells = <2>;
35 };
36 };
37
38 wkup_pmx0: pinmux@4301c000 {
39 compatible = "pinctrl-single";
40 /* Proxy 0 addressing */
41 reg = <0x00 0x4301c000 0x00 0x178>;
42 #pinctrl-cells = <1>;
43 pinctrl-single,register-width = <32>;
44 pinctrl-single,function-mask = <0xffffffff>;
45 };
46
47 wkup_uart0: serial@42300000 {
48 compatible = "ti,j721e-uart", "ti,am654-uart";
49 reg = <0x00 0x42300000 0x00 0x100>;
50 reg-shift = <2>;
51 reg-io-width = <4>;
52 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
53 clock-frequency = <48000000>;
54 current-speed = <115200>;
55 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
56 clocks = <&k3_clks 287 0>;
57 clock-names = "fclk";
58 };
59
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]60 wkup_i2c0: i2c@42120000 {
61 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
62 reg = <0x0 0x42120000 0x0 0x100>;
63 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
64 #address-cells = <1>;
65 #size-cells = <0>;
66 clock-names = "fck";
67 clocks = <&k3_clks 197 0>;
68 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
69 };
70
Lokesh Vutla5839b1c2019-06-13 10:29:53 +0530[diff] [blame]71 mcu_uart0: serial@40a00000 {
72 compatible = "ti,j721e-uart", "ti,am654-uart";
73 reg = <0x00 0x40a00000 0x00 0x100>;
74 reg-shift = <2>;
75 reg-io-width = <4>;
76 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
77 clock-frequency = <96000000>;
78 current-speed = <115200>;
79 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
80 clocks = <&k3_clks 149 0>;
81 clock-names = "fclk";
82 };
Lokesh Vutla1a128042019-09-04 16:01:37 +0530[diff] [blame]83
84 mcu_r5fss0: r5fss@41000000 {
85 compatible = "ti,j721e-r5fss";
86 lockstep-mode = <1>;
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <0x41000000 0x00 0x41000000 0x20000>,
90 <0x41400000 0x00 0x41400000 0x20000>;
91 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
92
93 mcu_r5fss0_core0: r5f@41000000 {
94 compatible = "ti,j721e-r5f";
95 reg = <0x41000000 0x00008000>,
96 <0x41010000 0x00008000>;
97 reg-names = "atcm", "btcm";
98 ti,sci = <&dmsc>;
99 ti,sci-dev-id = <250>;
100 ti,sci-proc-ids = <0x01 0xFF>;
101 resets = <&k3_reset 250 1>;
102 atcm-enable = <1>;
103 btcm-enable = <1>;
104 loczrama = <1>;
105 };
106
107 mcu_r5fss0_core1: r5f@41400000 {
108 compatible = "ti,j721e-r5f";
109 reg = <0x41400000 0x00008000>,
110 <0x41410000 0x00008000>;
111 reg-names = "atcm", "btcm";
112 ti,sci = <&dmsc>;
113 ti,sci-dev-id = <251>;
114 ti,sci-proc-ids = <0x02 0xFF>;
115 resets = <&k3_reset 251 1>;
116 atcm-enable = <1>;
117 btcm-enable = <1>;
118 loczrama = <1>;
119 };
120 };
Vignesh Raghavendra5ac11b52019-10-23 13:30:02 +0530[diff] [blame]121
122 fss: fss@47000000 {
123 compatible = "syscon", "simple-mfd";
124 reg = <0x0 0x47000000 0x0 0x100>;
125 #address-cells = <2>;
126 #size-cells = <2>;
127 ranges;
128
129 hbmc_mux: hbmc-mux {
130 compatible = "mmio-mux";
131 #mux-control-cells = <1>;
132 mux-reg-masks = <0x4 0x2>; /* HBMC select */
133 };
134
135 hbmc: hyperbus@47034000 {
136 compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
137 reg = <0x0 0x47034000 0x0 0x100>,
138 <0x5 0x00000000 0x1 0x0000000>;
139 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
140 #address-cells = <2>;
141 #size-cells = <1>;
142 mux-controls = <&hbmc_mux 0>;
143 assigned-clocks = <&k3_clks 102 0>;
144 assigned-clock-rates = <250000000>;
145 };
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]146
147 ospi0: spi@47040000 {
148 compatible = "ti,am654-ospi";
149 reg = <0x0 0x47040000 0x0 0x100>,
150 <0x5 0x00000000 0x1 0x0000000>;
151 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
152 cdns,fifo-depth = <256>;
153 cdns,fifo-width = <4>;
154 cdns,trigger-address = <0x0>;
155 clocks = <&k3_clks 103 0>;
156 assigned-clocks = <&k3_clks 103 0>;
157 assigned-clock-parents = <&k3_clks 103 2>;
158 assigned-clock-rates = <166666666>;
159 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 };
163
164 ospi1: spi@47050000 {
165 compatible = "ti,am654-ospi";
166 reg = <0x0 0x47050000 0x0 0x100>,
167 <0x7 0x00000000 0x1 0x00000000>;
168 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
169 cdns,fifo-depth = <256>;
170 cdns,fifo-width = <4>;
171 cdns,trigger-address = <0x0>;
172 clocks = <&k3_clks 104 0>;
Keerthye76ef1a2020-03-04 10:10:00 +0530[diff] [blame]173 assigned-clocks = <&k3_clks 104 0>;
174 assigned-clock-rates = <133333333>;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]175 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 };
Vignesh Raghavendra5ac11b52019-10-23 13:30:02 +0530[diff] [blame]179 };
Vignesh Raghavendrae421d092020-01-27 23:22:13 +0530[diff] [blame]180
181 mcu_i2c0: i2c@40b00000 {
182 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
183 reg = <0x0 0x40b00000 0x0 0x100>;
184 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 clock-names = "fck";
188 clocks = <&k3_clks 194 0>;
189 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
190 };
191
192 mcu_i2c1: i2c@40b10000 {
193 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
194 reg = <0x0 0x40b10000 0x0 0x100>;
195 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
196 #address-cells = <1>;
197 #size-cells = <0>;
198 clock-names = "fck";
199 clocks = <&k3_clks 195 0>;
200 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
201 };
Vignesh Raghavendra01250d82020-07-07 13:43:35 +0530[diff] [blame^]202
203 mcu_navss {
204 compatible = "simple-mfd";
205 #address-cells = <2>;
206 #size-cells = <2>;
207 ranges;
208 dma-coherent;
209 dma-ranges;
210
211 ti,sci-dev-id = <232>;
212
213 mcu_ringacc: ringacc@2b800000 {
214 compatible = "ti,am654-navss-ringacc";
215 reg = <0x0 0x2b800000 0x0 0x400000>,
216 <0x0 0x2b000000 0x0 0x400000>,
217 <0x0 0x28590000 0x0 0x100>,
218 <0x0 0x2a500000 0x0 0x40000>;
219 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
220 ti,num-rings = <286>;
221 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
222 ti,sci = <&dmsc>;
223 ti,sci-dev-id = <235>;
224 };
225
226 mcu_udmap: dma-controller@285c0000 {
227 compatible = "ti,j721e-navss-mcu-udmap";
228 reg = <0x0 0x285c0000 0x0 0x100>,
229 <0x0 0x2a800000 0x0 0x40000>,
230 <0x0 0x2aa00000 0x0 0x40000>;
231 reg-names = "gcfg", "rchanrt", "tchanrt";
232 #dma-cells = <1>;
233
234 ti,sci = <&dmsc>;
235 ti,sci-dev-id = <236>;
236 ti,ringacc = <&mcu_ringacc>;
237
238 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
239 <0x0f>; /* TX_HCHAN */
240 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
241 <0x0b>; /* RX_HCHAN */
242 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
243 };
244 };
Lokesh Vutla5839b1c2019-06-13 10:29:53 +0530[diff] [blame]245};