Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2018 Amarula Solutions. |
| 4 | * Author: Jagan Teki <jagan@amarulasolutions.com> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <clk-uclass.h> |
| 9 | #include <dm.h> |
| 10 | #include <errno.h> |
| 11 | #include <asm/arch/ccu.h> |
| 12 | #include <dt-bindings/clock/sun8i-v3s-ccu.h> |
| 13 | #include <dt-bindings/reset/sun8i-v3s-ccu.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 14 | #include <linux/bitops.h> |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 15 | |
| 16 | static struct ccu_clk_gate v3s_gates[] = { |
Andre Przywara | ddf33c1 | 2019-01-29 15:54:09 +0000 | [diff] [blame] | 17 | [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), |
| 18 | [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), |
| 19 | [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), |
Jagan Teki | bc12313 | 2019-02-27 20:02:06 +0530 | [diff] [blame] | 20 | [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 21 | [CLK_BUS_OTG] = GATE(0x060, BIT(24)), |
| 22 | |
Jagan Teki | 8cf08ea | 2018-12-30 21:29:24 +0530 | [diff] [blame] | 23 | [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), |
| 24 | [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), |
| 25 | [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), |
| 26 | |
Jagan Teki | bc12313 | 2019-02-27 20:02:06 +0530 | [diff] [blame] | 27 | [CLK_SPI0] = GATE(0x0a0, BIT(31)), |
| 28 | |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 29 | [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), |
| 30 | }; |
| 31 | |
| 32 | static struct ccu_reset v3s_resets[] = { |
| 33 | [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), |
| 34 | |
Andre Przywara | ddf33c1 | 2019-01-29 15:54:09 +0000 | [diff] [blame] | 35 | [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), |
| 36 | [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), |
| 37 | [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), |
Jagan Teki | bc12313 | 2019-02-27 20:02:06 +0530 | [diff] [blame] | 38 | [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 39 | [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), |
Jagan Teki | b490aa5 | 2018-12-30 21:37:31 +0530 | [diff] [blame] | 40 | |
| 41 | [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), |
| 42 | [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), |
| 43 | [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 44 | }; |
| 45 | |
| 46 | static const struct ccu_desc v3s_ccu_desc = { |
| 47 | .gates = v3s_gates, |
| 48 | .resets = v3s_resets, |
| 49 | }; |
| 50 | |
| 51 | static int v3s_clk_bind(struct udevice *dev) |
| 52 | { |
| 53 | return sunxi_reset_bind(dev, ARRAY_SIZE(v3s_resets)); |
| 54 | } |
| 55 | |
| 56 | static const struct udevice_id v3s_clk_ids[] = { |
| 57 | { .compatible = "allwinner,sun8i-v3s-ccu", |
| 58 | .data = (ulong)&v3s_ccu_desc }, |
Icenowy Zheng | 18e4ab6 | 2020-10-26 22:18:02 +0800 | [diff] [blame] | 59 | { .compatible = "allwinner,sun8i-v3-ccu", |
| 60 | .data = (ulong)&v3s_ccu_desc }, |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 61 | { } |
| 62 | }; |
| 63 | |
| 64 | U_BOOT_DRIVER(clk_sun8i_v3s) = { |
| 65 | .name = "sun8i_v3s_ccu", |
| 66 | .id = UCLASS_CLK, |
| 67 | .of_match = v3s_clk_ids, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 68 | .priv_auto = sizeof(struct ccu_priv), |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 69 | .ops = &sunxi_clk_ops, |
| 70 | .probe = sunxi_clk_probe, |
| 71 | .bind = v3s_clk_bind, |
| 72 | }; |