| Hai Pham | 9046b5f | 2023-02-28 22:22:03 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * ./arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h |
| 4 | * |
| 5 | * Copyright (C) 2021 Renesas Electronics Corp. |
| 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_ARCH_RCAR_GEN4_BASE_H |
| 9 | #define __ASM_ARCH_RCAR_GEN4_BASE_H |
| 10 | |
| 11 | /* |
| 12 | * R-Car (R8A779F0) I/O Addresses |
| 13 | */ |
| 14 | #define RWDT_BASE 0xE6020000 |
| 15 | #define SWDT_BASE 0xE6030000 |
| 16 | #define TMU_BASE 0xE61E0000 |
| 17 | |
| 18 | /* SCIF */ |
| 19 | #define SCIF0_BASE 0xE6E60000 |
| 20 | #define SCIF1_BASE 0xE6E68000 |
| 21 | #define SCIF2_BASE 0xE6E88000 |
| 22 | #define SCIF3_BASE 0xE6C50000 |
| 23 | #define SCIF4_BASE 0xE6C40000 |
| 24 | #define SCIF5_BASE 0xE6F30000 |
| 25 | |
| 26 | /* CPG */ |
| 27 | #define CPGWPR 0xE6150000 |
| 28 | #define CPGWPCR 0xE6150004 |
| 29 | |
| 30 | /* Reset */ |
| 31 | #define RST_BASE 0xE6160000 /* Domain0 */ |
| 32 | #define RST_SRESCR0 (RST_BASE + 0x18) |
| 33 | #define RST_SPRES 0x5AA58000 |
| 34 | |
| 35 | /* Arm Generic Timer */ |
| 36 | #define CNTCR_BASE 0xE6080000 |
| 37 | #define CNTFID0 (CNTCR_BASE + 0x020) |
| 38 | #define CNTCR_EN BIT(0) |
| 39 | |
| 40 | /* GICv3 */ |
| 41 | /* Distributor Registers */ |
| 42 | #define GICD_BASE 0xF1000000 |
| 43 | #define GICR_BASE (GICR_LPI_BASE) |
| 44 | |
| 45 | /* ReDistributor Registers for Control and Physical LPIs */ |
| 46 | #define GICR_LPI_BASE 0xF1060000 |
| 47 | #define GICR_WAKER 0x0014 |
| 48 | #define GICR_PWRR 0x0024 |
| 49 | #define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER) |
| 50 | #define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR) |
| 51 | |
| 52 | /* ReDistributor Registers for SGIs and PPIs */ |
| 53 | #define GICR_SGI_BASE 0xF1070000 |
| 54 | #define GICR_IGROUPR0 0x0080 |
| 55 | |
| 56 | #ifndef __ASSEMBLY__ |
| 57 | #include <asm/types.h> |
| 58 | #include <linux/bitops.h> |
| 59 | |
| 60 | /* RWDT */ |
| 61 | struct rcar_rwdt { |
| 62 | u32 rwtcnt; |
| 63 | u32 rwtcsra; |
| 64 | u32 rwtcsrb; |
| 65 | }; |
| 66 | |
| 67 | /* SWDT */ |
| 68 | struct rcar_swdt { |
| 69 | u32 swtcnt; |
| 70 | u32 swtcsra; |
| 71 | u32 swtcsrb; |
| 72 | }; |
| 73 | #endif |
| 74 | |
| 75 | #endif /* __ASM_ARCH_RCAR_GEN4_BASE_H */ |