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git01.mediatek.com / filogic / uboot / 0103212e48de4905fc1e79bf8f3cf7d0a4e577f3 / . / dts / upstream / src / arm64 / renesas / r8a779h0.dtsi
blob: 6d791024cabe1b94f01ad0514214a17ec613c075 [file] [log] [blame]
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the R-Car V4M (R8A779H0) SoC
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/renesas,r8a779h0-sysc.h>
11
12/ {
13 compatible = "renesas,r8a779h0";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cluster0_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
20
21 opp-500000000 {
22 opp-hz = /bits/ 64 <500000000>;
23 opp-microvolt = <825000>;
24 clock-latency-ns = <500000>;
25 };
26 opp-1000000000 {
27 opp-hz = /bits/ 64 <1000000000>;
28 opp-microvolt = <825000>;
29 clock-latency-ns = <500000>;
30 };
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 cpu-map {
38 cluster0 {
39 core0 {
40 cpu = <&a76_0>;
41 };
42 core1 {
43 cpu = <&a76_1>;
44 };
45 core2 {
46 cpu = <&a76_2>;
47 };
48 core3 {
49 cpu = <&a76_3>;
50 };
51 };
52 };
53
54 a76_0: cpu@0 {
55 compatible = "arm,cortex-a76";
56 reg = <0>;
57 device_type = "cpu";
58 power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
59 next-level-cache = <&L3_CA76>;
60 enable-method = "psci";
61 cpu-idle-states = <&CPU_SLEEP_0>;
62 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;
63 operating-points-v2 = <&cluster0_opp>;
64 };
65
66 a76_1: cpu@100 {
67 compatible = "arm,cortex-a76";
68 reg = <0x100>;
69 device_type = "cpu";
70 power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
71 next-level-cache = <&L3_CA76>;
72 enable-method = "psci";
73 cpu-idle-states = <&CPU_SLEEP_0>;
74 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;
75 operating-points-v2 = <&cluster0_opp>;
76 };
77
78 a76_2: cpu@200 {
79 compatible = "arm,cortex-a76";
80 reg = <0x200>;
81 device_type = "cpu";
82 power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
83 next-level-cache = <&L3_CA76>;
84 enable-method = "psci";
85 cpu-idle-states = <&CPU_SLEEP_0>;
86 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;
87 operating-points-v2 = <&cluster0_opp>;
88 };
89
90 a76_3: cpu@300 {
91 compatible = "arm,cortex-a76";
92 reg = <0x300>;
93 device_type = "cpu";
94 power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
95 next-level-cache = <&L3_CA76>;
96 enable-method = "psci";
97 cpu-idle-states = <&CPU_SLEEP_0>;
98 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;
99 operating-points-v2 = <&cluster0_opp>;
100 };
101
102 idle-states {
103 entry-method = "psci";
104
105 CPU_SLEEP_0: cpu-sleep-0 {
106 compatible = "arm,idle-state";
107 arm,psci-suspend-param = <0x0010000>;
108 local-timer-stop;
109 entry-latency-us = <400>;
110 exit-latency-us = <500>;
111 min-residency-us = <4000>;
112 };
113 };
114
115 L3_CA76: cache-controller {
116 compatible = "cache";
117 power-domains = <&sysc R8A779H0_PD_A2E0D0>;
118 cache-unified;
119 cache-level = <3>;
120 };
121 };
122
123 extal_clk: extal-clk {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 /* This value must be overridden by the board */
127 clock-frequency = <0>;
128 };
129
130 extalr_clk: extalr-clk {
131 compatible = "fixed-clock";
132 #clock-cells = <0>;
133 /* This value must be overridden by the board */
134 clock-frequency = <0>;
135 };
136
137 pmu-a76 {
138 compatible = "arm,cortex-a76-pmu";
139 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
140 };
141
142 psci {
143 compatible = "arm,psci-1.0", "arm,psci-0.2";
144 method = "smc";
145 };
146
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]147 /* External SCIF clocks - to be overridden by boards that provide them */
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]148 scif_clk: scif-clk {
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 clock-frequency = <0>;
152 };
153
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]154 scif_clk2: scif-clk2 {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <0>;
158 };
159
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]160 soc: soc {
161 compatible = "simple-bus";
162 interrupt-parent = <&gic>;
163 #address-cells = <2>;
164 #size-cells = <2>;
165 ranges;
166
167 rwdt: watchdog@e6020000 {
168 compatible = "renesas,r8a779h0-wdt",
169 "renesas,rcar-gen4-wdt";
170 reg = <0 0xe6020000 0 0x0c>;
171 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&cpg CPG_MOD 907>;
173 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
174 resets = <&cpg 907>;
175 status = "disabled";
176 };
177
178 pfc: pinctrl@e6050000 {
179 compatible = "renesas,pfc-r8a779h0";
180 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
181 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
182 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
183 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
184 };
185
186 gpio0: gpio@e6050180 {
187 compatible = "renesas,gpio-r8a779h0",
188 "renesas,rcar-gen4-gpio";
189 reg = <0 0xe6050180 0 0x54>;
190 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
191 #gpio-cells = <2>;
192 gpio-controller;
193 gpio-ranges = <&pfc 0 0 19>;
194 #interrupt-cells = <2>;
195 interrupt-controller;
196 clocks = <&cpg CPG_MOD 915>;
197 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
198 resets = <&cpg 915>;
199 };
200
201 gpio1: gpio@e6050980 {
202 compatible = "renesas,gpio-r8a779h0",
203 "renesas,rcar-gen4-gpio";
204 reg = <0 0xe6050980 0 0x54>;
205 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
206 #gpio-cells = <2>;
207 gpio-controller;
208 gpio-ranges = <&pfc 0 32 30>;
209 #interrupt-cells = <2>;
210 interrupt-controller;
211 clocks = <&cpg CPG_MOD 915>;
212 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
213 resets = <&cpg 915>;
214 };
215
216 gpio2: gpio@e6058180 {
217 compatible = "renesas,gpio-r8a779h0",
218 "renesas,rcar-gen4-gpio";
219 reg = <0 0xe6058180 0 0x54>;
220 interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
221 #gpio-cells = <2>;
222 gpio-controller;
223 gpio-ranges = <&pfc 0 64 20>;
224 #interrupt-cells = <2>;
225 interrupt-controller;
226 clocks = <&cpg CPG_MOD 916>;
227 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
228 resets = <&cpg 916>;
229 };
230
231 gpio3: gpio@e6058980 {
232 compatible = "renesas,gpio-r8a779h0",
233 "renesas,rcar-gen4-gpio";
234 reg = <0 0xe6058980 0 0x54>;
235 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
236 #gpio-cells = <2>;
237 gpio-controller;
238 gpio-ranges = <&pfc 0 96 32>;
239 #interrupt-cells = <2>;
240 interrupt-controller;
241 clocks = <&cpg CPG_MOD 916>;
242 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
243 resets = <&cpg 916>;
244 };
245
246 gpio4: gpio@e6060180 {
247 compatible = "renesas,gpio-r8a779h0",
248 "renesas,rcar-gen4-gpio";
249 reg = <0 0xe6060180 0 0x54>;
250 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
251 #gpio-cells = <2>;
252 gpio-controller;
253 gpio-ranges = <&pfc 0 128 25>;
254 #interrupt-cells = <2>;
255 interrupt-controller;
256 clocks = <&cpg CPG_MOD 917>;
257 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
258 resets = <&cpg 917>;
259 };
260
261 gpio5: gpio@e6060980 {
262 compatible = "renesas,gpio-r8a779h0",
263 "renesas,rcar-gen4-gpio";
264 reg = <0 0xe6060980 0 0x54>;
265 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
266 #gpio-cells = <2>;
267 gpio-controller;
268 gpio-ranges = <&pfc 0 160 21>;
269 #interrupt-cells = <2>;
270 interrupt-controller;
271 clocks = <&cpg CPG_MOD 917>;
272 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
273 resets = <&cpg 917>;
274 };
275
276 gpio6: gpio@e6061180 {
277 compatible = "renesas,gpio-r8a779h0",
278 "renesas,rcar-gen4-gpio";
279 reg = <0 0xe6061180 0 0x54>;
280 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
281 #gpio-cells = <2>;
282 gpio-controller;
283 gpio-ranges = <&pfc 0 192 21>;
284 #interrupt-cells = <2>;
285 interrupt-controller;
286 clocks = <&cpg CPG_MOD 917>;
287 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
288 resets = <&cpg 917>;
289 };
290
291 gpio7: gpio@e6061980 {
292 compatible = "renesas,gpio-r8a779h0",
293 "renesas,rcar-gen4-gpio";
294 reg = <0 0xe6061980 0 0x54>;
295 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
296 #gpio-cells = <2>;
297 gpio-controller;
298 gpio-ranges = <&pfc 0 224 21>;
299 #interrupt-cells = <2>;
300 interrupt-controller;
301 clocks = <&cpg CPG_MOD 917>;
302 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
303 resets = <&cpg 917>;
304 };
305
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]306 cmt0: timer@e60f0000 {
307 compatible = "renesas,r8a779h0-cmt0",
308 "renesas,rcar-gen4-cmt0";
309 reg = <0 0xe60f0000 0 0x1004>;
310 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&cpg CPG_MOD 910>;
313 clock-names = "fck";
314 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
315 resets = <&cpg 910>;
316 status = "disabled";
317 };
318
319 cmt1: timer@e6130000 {
320 compatible = "renesas,r8a779h0-cmt1",
321 "renesas,rcar-gen4-cmt1";
322 reg = <0 0xe6130000 0 0x1004>;
323 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cpg CPG_MOD 911>;
332 clock-names = "fck";
333 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
334 resets = <&cpg 911>;
335 status = "disabled";
336 };
337
338 cmt2: timer@e6140000 {
339 compatible = "renesas,r8a779h0-cmt1",
340 "renesas,rcar-gen4-cmt1";
341 reg = <0 0xe6140000 0 0x1004>;
342 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&cpg CPG_MOD 912>;
351 clock-names = "fck";
352 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
353 resets = <&cpg 912>;
354 status = "disabled";
355 };
356
357 cmt3: timer@e6148000 {
358 compatible = "renesas,r8a779h0-cmt1",
359 "renesas,rcar-gen4-cmt1";
360 reg = <0 0xe6148000 0 0x1004>;
361 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&cpg CPG_MOD 913>;
370 clock-names = "fck";
371 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
372 resets = <&cpg 913>;
373 status = "disabled";
374 };
375
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]376 cpg: clock-controller@e6150000 {
377 compatible = "renesas,r8a779h0-cpg-mssr";
378 reg = <0 0xe6150000 0 0x4000>;
379 clocks = <&extal_clk>, <&extalr_clk>;
380 clock-names = "extal", "extalr";
381 #clock-cells = <2>;
382 #power-domain-cells = <0>;
383 #reset-cells = <1>;
384 };
385
386 rst: reset-controller@e6160000 {
387 compatible = "renesas,r8a779h0-rst";
388 reg = <0 0xe6160000 0 0x4000>;
389 };
390
391 sysc: system-controller@e6180000 {
392 compatible = "renesas,r8a779h0-sysc";
393 reg = <0 0xe6180000 0 0x4000>;
394 #power-domain-cells = <1>;
395 };
396
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]397 tsc: thermal@e6198000 {
398 compatible = "renesas,r8a779h0-thermal";
399 reg = <0 0xe6198000 0 0x200>,
400 <0 0xe61a0000 0 0x200>;
401 clocks = <&cpg CPG_MOD 919>;
402 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
403 resets = <&cpg 919>;
404 #thermal-sensor-cells = <1>;
405 };
406
407 intc_ex: interrupt-controller@e61c0000 {
408 compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc";
409 #interrupt-cells = <2>;
410 interrupt-controller;
411 reg = <0 0xe61c0000 0 0x200>;
412 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cpg CPG_MOD 611>;
419 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
420 resets = <&cpg 611>;
421 };
422
423 tmu0: timer@e61e0000 {
424 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
425 reg = <0 0xe61e0000 0 0x30>;
426 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "tuni0", "tuni1", "tuni2";
430 clocks = <&cpg CPG_MOD 713>;
431 clock-names = "fck";
432 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
433 resets = <&cpg 713>;
434 status = "disabled";
435 };
436
437 tmu1: timer@e6fc0000 {
438 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
439 reg = <0 0xe6fc0000 0 0x30>;
440 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
445 clocks = <&cpg CPG_MOD 714>;
446 clock-names = "fck";
447 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
448 resets = <&cpg 714>;
449 status = "disabled";
450 };
451
452 tmu2: timer@e6fd0000 {
453 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
454 reg = <0 0xe6fd0000 0 0x30>;
455 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
459 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
460 clocks = <&cpg CPG_MOD 715>;
461 clock-names = "fck";
462 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
463 resets = <&cpg 715>;
464 status = "disabled";
465 };
466
467 tmu3: timer@e6fe0000 {
468 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
469 reg = <0 0xe6fe0000 0 0x30>;
470 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
475 clocks = <&cpg CPG_MOD 716>;
476 clock-names = "fck";
477 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
478 resets = <&cpg 716>;
479 status = "disabled";
480 };
481
482 tmu4: timer@ffc00000 {
483 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
484 reg = <0 0xffc00000 0 0x30>;
485 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
489 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
490 clocks = <&cpg CPG_MOD 717>;
491 clock-names = "fck";
492 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
493 resets = <&cpg 717>;
494 status = "disabled";
495 };
496
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]497 i2c0: i2c@e6500000 {
498 compatible = "renesas,i2c-r8a779h0",
499 "renesas,rcar-gen4-i2c";
500 reg = <0 0xe6500000 0 0x40>;
501 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cpg CPG_MOD 518>;
503 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
504 resets = <&cpg 518>;
505 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
506 <&dmac2 0x91>, <&dmac2 0x90>;
507 dma-names = "tx", "rx", "tx", "rx";
508 i2c-scl-internal-delay-ns = <110>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 status = "disabled";
512 };
513
514 i2c1: i2c@e6508000 {
515 compatible = "renesas,i2c-r8a779h0",
516 "renesas,rcar-gen4-i2c";
517 reg = <0 0xe6508000 0 0x40>;
518 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&cpg CPG_MOD 519>;
520 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
521 resets = <&cpg 519>;
522 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
523 <&dmac2 0x93>, <&dmac2 0x92>;
524 dma-names = "tx", "rx", "tx", "rx";
525 i2c-scl-internal-delay-ns = <110>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528 status = "disabled";
529 };
530
531 i2c2: i2c@e6510000 {
532 compatible = "renesas,i2c-r8a779h0",
533 "renesas,rcar-gen4-i2c";
534 reg = <0 0xe6510000 0 0x40>;
535 interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&cpg CPG_MOD 520>;
537 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
538 resets = <&cpg 520>;
539 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
540 <&dmac2 0x95>, <&dmac2 0x94>;
541 dma-names = "tx", "rx", "tx", "rx";
542 i2c-scl-internal-delay-ns = <110>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 status = "disabled";
546 };
547
548 i2c3: i2c@e66d0000 {
549 compatible = "renesas,i2c-r8a779h0",
550 "renesas,rcar-gen4-i2c";
551 reg = <0 0xe66d0000 0 0x40>;
552 interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 521>;
554 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
555 resets = <&cpg 521>;
556 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
557 <&dmac2 0x97>, <&dmac2 0x96>;
558 dma-names = "tx", "rx", "tx", "rx";
559 i2c-scl-internal-delay-ns = <110>;
560 #address-cells = <1>;
561 #size-cells = <0>;
562 status = "disabled";
563 };
564
565 hscif0: serial@e6540000 {
566 compatible = "renesas,hscif-r8a779h0",
567 "renesas,rcar-gen4-hscif", "renesas,hscif";
568 reg = <0 0xe6540000 0 0x60>;
569 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 514>,
571 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
572 <&scif_clk>;
573 clock-names = "fck", "brg_int", "scif_clk";
574 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
575 resets = <&cpg 514>;
576 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
577 <&dmac2 0x31>, <&dmac2 0x30>;
578 dma-names = "tx", "rx", "tx", "rx";
579 status = "disabled";
580 };
581
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]582 hscif1: serial@e6550000 {
583 compatible = "renesas,hscif-r8a779h0",
584 "renesas,rcar-gen4-hscif", "renesas,hscif";
585 reg = <0 0xe6550000 0 0x60>;
586 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cpg CPG_MOD 515>,
588 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
589 <&scif_clk>;
590 clock-names = "fck", "brg_int", "scif_clk";
591 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
592 resets = <&cpg 515>;
593 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
594 <&dmac2 0x33>, <&dmac2 0x32>;
595 dma-names = "tx", "rx", "tx", "rx";
596 status = "disabled";
597 };
598
599 hscif2: serial@e6560000 {
600 compatible = "renesas,hscif-r8a779h0",
601 "renesas,rcar-gen4-hscif", "renesas,hscif";
602 reg = <0 0xe6560000 0 0x60>;
603 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 516>,
605 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
606 <&scif_clk2>;
607 clock-names = "fck", "brg_int", "scif_clk";
608 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
609 resets = <&cpg 516>;
610 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
611 <&dmac2 0x35>, <&dmac2 0x34>;
612 dma-names = "tx", "rx", "tx", "rx";
613 status = "disabled";
614 };
615
616 hscif3: serial@e66a0000 {
617 compatible = "renesas,hscif-r8a779h0",
618 "renesas,rcar-gen4-hscif", "renesas,hscif";
619 reg = <0 0xe66a0000 0 0x60>;
620 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cpg CPG_MOD 517>,
622 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
623 <&scif_clk>;
624 clock-names = "fck", "brg_int", "scif_clk";
625 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
626 resets = <&cpg 517>;
627 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
628 <&dmac2 0x37>, <&dmac2 0x36>;
629 dma-names = "tx", "rx", "tx", "rx";
630 status = "disabled";
631 };
632
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]633 avb0: ethernet@e6800000 {
634 compatible = "renesas,etheravb-r8a779h0",
635 "renesas,etheravb-rcar-gen4";
636 reg = <0 0xe6800000 0 0x1000>;
637 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
662 interrupt-names = "ch0", "ch1", "ch2", "ch3",
663 "ch4", "ch5", "ch6", "ch7",
664 "ch8", "ch9", "ch10", "ch11",
665 "ch12", "ch13", "ch14", "ch15",
666 "ch16", "ch17", "ch18", "ch19",
667 "ch20", "ch21", "ch22", "ch23",
668 "ch24";
669 clocks = <&cpg CPG_MOD 211>;
670 clock-names = "fck";
671 power-domains = <&sysc R8A779H0_PD_C4>;
672 resets = <&cpg 211>;
673 phy-mode = "rgmii";
674 rx-internal-delay-ps = <0>;
675 tx-internal-delay-ps = <0>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]676 iommus = <&ipmmu_hc 0>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]677 #address-cells = <1>;
678 #size-cells = <0>;
679 status = "disabled";
680 };
681
682 avb1: ethernet@e6810000 {
683 compatible = "renesas,etheravb-r8a779h0",
684 "renesas,etheravb-rcar-gen4";
685 reg = <0 0xe6810000 0 0x1000>;
686 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
711 interrupt-names = "ch0", "ch1", "ch2", "ch3",
712 "ch4", "ch5", "ch6", "ch7",
713 "ch8", "ch9", "ch10", "ch11",
714 "ch12", "ch13", "ch14", "ch15",
715 "ch16", "ch17", "ch18", "ch19",
716 "ch20", "ch21", "ch22", "ch23",
717 "ch24";
718 clocks = <&cpg CPG_MOD 212>;
719 clock-names = "fck";
720 power-domains = <&sysc R8A779H0_PD_C4>;
721 resets = <&cpg 212>;
722 phy-mode = "rgmii";
723 rx-internal-delay-ps = <0>;
724 tx-internal-delay-ps = <0>;
725 #address-cells = <1>;
726 #size-cells = <0>;
727 status = "disabled";
728 };
729
730 avb2: ethernet@e6820000 {
731 compatible = "renesas,etheravb-r8a779h0",
732 "renesas,etheravb-rcar-gen4";
733 reg = <0 0xe6820000 0 0x1000>;
734 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
759 interrupt-names = "ch0", "ch1", "ch2", "ch3",
760 "ch4", "ch5", "ch6", "ch7",
761 "ch8", "ch9", "ch10", "ch11",
762 "ch12", "ch13", "ch14", "ch15",
763 "ch16", "ch17", "ch18", "ch19",
764 "ch20", "ch21", "ch22", "ch23",
765 "ch24";
766 clocks = <&cpg CPG_MOD 213>;
767 clock-names = "fck";
768 power-domains = <&sysc R8A779H0_PD_C4>;
769 resets = <&cpg 213>;
770 phy-mode = "rgmii";
771 rx-internal-delay-ps = <0>;
772 tx-internal-delay-ps = <0>;
773 #address-cells = <1>;
774 #size-cells = <0>;
775 status = "disabled";
776 };
777
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]778 scif0: serial@e6e60000 {
779 compatible = "renesas,scif-r8a779h0",
780 "renesas,rcar-gen4-scif", "renesas,scif";
781 reg = <0 0xe6e60000 0 64>;
782 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&cpg CPG_MOD 702>,
784 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
785 <&scif_clk>;
786 clock-names = "fck", "brg_int", "scif_clk";
787 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
788 resets = <&cpg 702>;
789 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
790 <&dmac2 0x51>, <&dmac2 0x50>;
791 dma-names = "tx", "rx", "tx", "rx";
792 status = "disabled";
793 };
794
795 scif1: serial@e6e68000 {
796 compatible = "renesas,scif-r8a779h0",
797 "renesas,rcar-gen4-scif", "renesas,scif";
798 reg = <0 0xe6e68000 0 64>;
799 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&cpg CPG_MOD 703>,
801 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
802 <&scif_clk>;
803 clock-names = "fck", "brg_int", "scif_clk";
804 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
805 resets = <&cpg 703>;
806 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
807 <&dmac2 0x53>, <&dmac2 0x52>;
808 dma-names = "tx", "rx", "tx", "rx";
809 status = "disabled";
810 };
811
812 scif3: serial@e6c50000 {
813 compatible = "renesas,scif-r8a779h0",
814 "renesas,rcar-gen4-scif", "renesas,scif";
815 reg = <0 0xe6c50000 0 64>;
816 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&cpg CPG_MOD 704>,
818 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
819 <&scif_clk>;
820 clock-names = "fck", "brg_int", "scif_clk";
821 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
822 resets = <&cpg 704>;
823 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
824 <&dmac2 0x57>, <&dmac2 0x56>;
825 dma-names = "tx", "rx", "tx", "rx";
826 status = "disabled";
827 };
828
829 scif4: serial@e6c40000 {
830 compatible = "renesas,scif-r8a779h0",
831 "renesas,rcar-gen4-scif", "renesas,scif";
832 reg = <0 0xe6c40000 0 64>;
833 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&cpg CPG_MOD 705>,
835 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
836 <&scif_clk2>;
837 clock-names = "fck", "brg_int", "scif_clk";
838 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
839 resets = <&cpg 705>;
840 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
841 <&dmac2 0x59>, <&dmac2 0x58>;
842 dma-names = "tx", "rx", "tx", "rx";
843 status = "disabled";
844 };
845
846 msiof0: spi@e6e90000 {
847 compatible = "renesas,msiof-r8a779h0",
848 "renesas,rcar-gen4-msiof";
849 reg = <0 0xe6e90000 0 0x0064>;
850 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&cpg CPG_MOD 618>;
852 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
853 <&dmac2 0x41>, <&dmac2 0x40>;
854 dma-names = "tx", "rx", "tx", "rx";
855 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
856 resets = <&cpg 618>;
857 #address-cells = <1>;
858 #size-cells = <0>;
859 status = "disabled";
860 };
861
862 msiof1: spi@e6ea0000 {
863 compatible = "renesas,msiof-r8a779h0",
864 "renesas,rcar-gen4-msiof";
865 reg = <0 0xe6ea0000 0 0x0064>;
866 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&cpg CPG_MOD 619>;
868 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
869 <&dmac2 0x43>, <&dmac2 0x42>;
870 dma-names = "tx", "rx", "tx", "rx";
871 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
872 resets = <&cpg 619>;
873 #address-cells = <1>;
874 #size-cells = <0>;
875 status = "disabled";
876 };
877
878 msiof2: spi@e6c00000 {
879 compatible = "renesas,msiof-r8a779h0",
880 "renesas,rcar-gen4-msiof";
881 reg = <0 0xe6c00000 0 0x0064>;
882 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&cpg CPG_MOD 620>;
884 dmas = <&dmac1 0x45>, <&dmac1 0x44>,
885 <&dmac2 0x45>, <&dmac2 0x44>;
886 dma-names = "tx", "rx", "tx", "rx";
887 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
888 resets = <&cpg 620>;
889 #address-cells = <1>;
890 #size-cells = <0>;
891 status = "disabled";
892 };
893
894 msiof3: spi@e6c10000 {
895 compatible = "renesas,msiof-r8a779h0",
896 "renesas,rcar-gen4-msiof";
897 reg = <0 0xe6c10000 0 0x0064>;
898 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&cpg CPG_MOD 621>;
900 dmas = <&dmac1 0x47>, <&dmac1 0x46>,
901 <&dmac2 0x47>, <&dmac2 0x46>;
902 dma-names = "tx", "rx", "tx", "rx";
903 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
904 resets = <&cpg 621>;
905 #address-cells = <1>;
906 #size-cells = <0>;
907 status = "disabled";
908 };
909
910 msiof4: spi@e6c20000 {
911 compatible = "renesas,msiof-r8a779h0",
912 "renesas,rcar-gen4-msiof";
913 reg = <0 0xe6c20000 0 0x0064>;
914 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&cpg CPG_MOD 622>;
916 dmas = <&dmac1 0x49>, <&dmac1 0x48>,
917 <&dmac2 0x49>, <&dmac2 0x48>;
918 dma-names = "tx", "rx", "tx", "rx";
919 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
920 resets = <&cpg 622>;
921 #address-cells = <1>;
922 #size-cells = <0>;
923 status = "disabled";
924 };
925
926 msiof5: spi@e6c28000 {
927 compatible = "renesas,msiof-r8a779h0",
928 "renesas,rcar-gen4-msiof";
929 reg = <0 0xe6c28000 0 0x0064>;
930 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&cpg CPG_MOD 623>;
932 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>,
933 <&dmac2 0x4b>, <&dmac2 0x4a>;
934 dma-names = "tx", "rx", "tx", "rx";
935 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
936 resets = <&cpg 623>;
937 #address-cells = <1>;
938 #size-cells = <0>;
939 status = "disabled";
940 };
941
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]942 dmac1: dma-controller@e7350000 {
943 compatible = "renesas,dmac-r8a779h0",
944 "renesas,rcar-gen4-dmac";
945 reg = <0 0xe7350000 0 0x1000>,
946 <0 0xe7300000 0 0x10000>;
947 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
964 interrupt-names = "error",
965 "ch0", "ch1", "ch2", "ch3", "ch4",
966 "ch5", "ch6", "ch7", "ch8", "ch9",
967 "ch10", "ch11", "ch12", "ch13",
968 "ch14", "ch15";
969 clocks = <&cpg CPG_MOD 709>;
970 clock-names = "fck";
971 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
972 resets = <&cpg 709>;
973 #dma-cells = <1>;
974 dma-channels = <16>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]975 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
976 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
977 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
978 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
979 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
980 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
981 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
982 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]983 };
984
985 dmac2: dma-controller@e7351000 {
986 compatible = "renesas,dmac-r8a779h0",
987 "renesas,rcar-gen4-dmac";
988 reg = <0 0xe7351000 0 0x1000>,
989 <0 0xe7310000 0 0x10000>;
990 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
999 interrupt-names = "error",
1000 "ch0", "ch1", "ch2", "ch3", "ch4",
1001 "ch5", "ch6", "ch7";
1002 clocks = <&cpg CPG_MOD 710>;
1003 clock-names = "fck";
1004 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1005 resets = <&cpg 710>;
1006 #dma-cells = <1>;
1007 dma-channels = <8>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1008 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
1009 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
1010 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
1011 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1012 };
1013
1014 mmc0: mmc@ee140000 {
1015 compatible = "renesas,sdhi-r8a779h0",
1016 "renesas,rcar-gen4-sdhi";
1017 reg = <0 0xee140000 0 0x2000>;
1018 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&cpg CPG_MOD 706>,
1020 <&cpg CPG_CORE R8A779H0_CLK_SD0H>;
1021 clock-names = "core", "clkh";
1022 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1023 resets = <&cpg 706>;
1024 max-frequency = <200000000>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1025 iommus = <&ipmmu_ds0 32>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1026 status = "disabled";
1027 };
1028
1029 rpc: spi@ee200000 {
1030 compatible = "renesas,r8a779h0-rpc-if",
1031 "renesas,rcar-gen4-rpc-if";
1032 reg = <0 0xee200000 0 0x200>,
1033 <0 0x08000000 0 0x04000000>,
1034 <0 0xee208000 0 0x100>;
1035 reg-names = "regs", "dirmap", "wbuf";
1036 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&cpg CPG_MOD 629>;
1038 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1039 resets = <&cpg 629>;
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042 status = "disabled";
1043 };
1044
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1045 ipmmu_rt0: iommu@ee480000 {
1046 compatible = "renesas,ipmmu-r8a779h0",
1047 "renesas,rcar-gen4-ipmmu-vmsa";
1048 reg = <0 0xee480000 0 0x20000>;
1049 renesas,ipmmu-main = <&ipmmu_mm>;
1050 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1051 #iommu-cells = <1>;
1052 };
1053
1054 ipmmu_rt1: iommu@ee4c0000 {
1055 compatible = "renesas,ipmmu-r8a779h0",
1056 "renesas,rcar-gen4-ipmmu-vmsa";
1057 reg = <0 0xee4c0000 0 0x20000>;
1058 renesas,ipmmu-main = <&ipmmu_mm>;
1059 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1060 #iommu-cells = <1>;
1061 };
1062
1063 ipmmu_ds0: iommu@eed00000 {
1064 compatible = "renesas,ipmmu-r8a779h0",
1065 "renesas,rcar-gen4-ipmmu-vmsa";
1066 reg = <0 0xeed00000 0 0x20000>;
1067 renesas,ipmmu-main = <&ipmmu_mm>;
1068 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1069 #iommu-cells = <1>;
1070 };
1071
1072 ipmmu_hc: iommu@eed40000 {
1073 compatible = "renesas,ipmmu-r8a779h0",
1074 "renesas,rcar-gen4-ipmmu-vmsa";
1075 reg = <0 0xeed40000 0 0x20000>;
1076 renesas,ipmmu-main = <&ipmmu_mm>;
1077 power-domains = <&sysc R8A779H0_PD_C4>;
1078 #iommu-cells = <1>;
1079 };
1080
1081 ipmmu_ir: iommu@eed80000 {
1082 compatible = "renesas,ipmmu-r8a779h0",
1083 "renesas,rcar-gen4-ipmmu-vmsa";
1084 reg = <0 0xeed80000 0 0x20000>;
1085 renesas,ipmmu-main = <&ipmmu_mm>;
1086 power-domains = <&sysc R8A779H0_PD_C4>;
1087 #iommu-cells = <1>;
1088 };
1089
1090 ipmmu_vc: iommu@eedc0000 {
1091 compatible = "renesas,ipmmu-r8a779h0",
1092 "renesas,rcar-gen4-ipmmu-vmsa";
1093 reg = <0 0xeedc0000 0 0x20000>;
1094 renesas,ipmmu-main = <&ipmmu_mm>;
1095 power-domains = <&sysc R8A779H0_PD_C4>;
1096 #iommu-cells = <1>;
1097 };
1098
1099 ipmmu_3dg: iommu@eee00000 {
1100 compatible = "renesas,ipmmu-r8a779h0",
1101 "renesas,rcar-gen4-ipmmu-vmsa";
1102 reg = <0 0xeee00000 0 0x20000>;
1103 renesas,ipmmu-main = <&ipmmu_mm>;
1104 power-domains = <&sysc R8A779H0_PD_C4>;
1105 #iommu-cells = <1>;
1106 };
1107
1108 ipmmu_vi0: iommu@eee80000 {
1109 compatible = "renesas,ipmmu-r8a779h0",
1110 "renesas,rcar-gen4-ipmmu-vmsa";
1111 reg = <0 0xeee80000 0 0x20000>;
1112 renesas,ipmmu-main = <&ipmmu_mm>;
1113 power-domains = <&sysc R8A779H0_PD_C4>;
1114 #iommu-cells = <1>;
1115 };
1116
1117 ipmmu_vi1: iommu@eeec0000 {
1118 compatible = "renesas,ipmmu-r8a779h0",
1119 "renesas,rcar-gen4-ipmmu-vmsa";
1120 reg = <0 0xeeec0000 0 0x20000>;
1121 renesas,ipmmu-main = <&ipmmu_mm>;
1122 power-domains = <&sysc R8A779H0_PD_C4>;
1123 #iommu-cells = <1>;
1124 };
1125
1126 ipmmu_vip0: iommu@eef00000 {
1127 compatible = "renesas,ipmmu-r8a779h0",
1128 "renesas,rcar-gen4-ipmmu-vmsa";
1129 reg = <0 0xeef00000 0 0x20000>;
1130 renesas,ipmmu-main = <&ipmmu_mm>;
1131 power-domains = <&sysc R8A779H0_PD_C4>;
1132 #iommu-cells = <1>;
1133 };
1134
1135 ipmmu_mm: iommu@eefc0000 {
1136 compatible = "renesas,ipmmu-r8a779h0",
1137 "renesas,rcar-gen4-ipmmu-vmsa";
1138 reg = <0 0xeefc0000 0 0x20000>;
1139 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1141 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1142 #iommu-cells = <1>;
1143 };
1144
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1145 gic: interrupt-controller@f1000000 {
1146 compatible = "arm,gic-v3";
1147 #interrupt-cells = <3>;
1148 #address-cells = <0>;
1149 interrupt-controller;
1150 reg = <0x0 0xf1000000 0 0x20000>,
1151 <0x0 0xf1060000 0 0x110000>;
1152 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1153 };
1154
1155 prr: chipid@fff00044 {
1156 compatible = "renesas,prr";
1157 reg = <0 0xfff00044 0 4>;
1158 };
1159 };
1160
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1161 thermal-zones {
1162 sensor_thermal_cr52: sensor1-thermal {
1163 polling-delay-passive = <250>;
1164 polling-delay = <1000>;
1165 thermal-sensors = <&tsc 0>;
1166
1167 trips {
1168 sensor1_crit: sensor1-crit {
1169 temperature = <120000>;
1170 hysteresis = <1000>;
1171 type = "critical";
1172 };
1173 };
1174 };
1175
1176 sensor_thermal_ca76: sensor2-thermal {
1177 polling-delay-passive = <250>;
1178 polling-delay = <1000>;
1179 thermal-sensors = <&tsc 1>;
1180
1181 trips {
1182 sensor2_crit: sensor2-crit {
1183 temperature = <120000>;
1184 hysteresis = <1000>;
1185 type = "critical";
1186 };
1187 };
1188 };
1189 };
1190
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1191 timer {
1192 compatible = "arm,armv8-timer";
1193 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1194 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1195 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1196 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
1197 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
1198 };
1199};