Wan Yee Lau | e249d54 | 2024-02-05 11:47:16 +0800 | [diff] [blame] | 1 | * Firewall and privilege register settings in device tree |
| 2 | |
| 3 | Required properties: |
| 4 | -------------------- |
| 5 | |
| 6 | - compatible: should contain "intel,socfpga-dtreg" |
| 7 | - reg: Physical base address and size of block register. |
| 8 | - intel,offset-settings: 32-bit offset address of block register, |
| 9 | followed by 32-bit value settings and |
| 10 | the masking bits, only masking bit |
| 11 | set to 1 allows modification. |
| 12 | |
| 13 | The device tree node which describes secure and privilege register access |
| 14 | configuration in compile time. |
| 15 | |
| 16 | Most of these registers are expected to work except for the case which some |
| 17 | registers configuration are required for granting access to some other |
| 18 | registers, for example CCU registers have to be properly configured before |
| 19 | allowing register configuration access to fpga2sdram firewall as shown in |
| 20 | below example. |
| 21 | |
| 22 | Some registers depend on runtime data for proper configuration are expected |
| 23 | to be part of driver that generating these data for example configuration for |
| 24 | soc_noc_fw_ddr_mpu_inst_0_ddr_scr block register depend on DDR size parsed from |
| 25 | memory device tree node. |
| 26 | |
| 27 | Please refer details of tested examples below for both fpga2sdram and QoS |
| 28 | configuration with default reset value and the comments. |
| 29 | |
| 30 | Example: |
| 31 | -------- |
| 32 | |
| 33 | Configuration for multiple dtreg node support in device tree: |
| 34 | |
| 35 | socfpga_dtreg0: socfpga-dtreg0 { |
| 36 | compatible = "intel,socfpga-dtreg"; |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <1>; |
| 39 | bootph-all; |
| 40 | |
| 41 | coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 { |
| 42 | reg = <0xf7100200 0x00000014>; |
| 43 | intel,offset-settings = |
| 44 | /* |
| 45 | * Disable ocram security at CCU for |
| 46 | * non secure access |
| 47 | */ |
| 48 | <0x0000004 0x8000ffff 0xe007ffff>, |
| 49 | <0x0000008 0x8000ffff 0xe007ffff>, |
| 50 | <0x000000c 0x8000ffff 0xe007ffff>, |
| 51 | <0x0000010 0x8000ffff 0xe007ffff>; |
| 52 | bootph-all; |
| 53 | }; |
| 54 | }; |
| 55 | |
| 56 | socfpga_dtreg1: socfpga-dtreg1 { |
| 57 | compatible = "intel,socfpga-dtreg"; |
| 58 | #address-cells = <1>; |
| 59 | #size-cells = <1>; |
| 60 | bootph-all; |
| 61 | |
| 62 | soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { |
| 63 | reg = <0xf8020000 0x0000001c>; |
| 64 | intel,offset-settings = |
| 65 | /* Disable MPFE firewall for SMMU */ |
| 66 | <0x00000000 0x00010101 0x00010101>, |
| 67 | /* |
| 68 | * Disable MPFE firewall for HMC |
| 69 | * adapter |
| 70 | */ |
| 71 | <0x00000004 0x00000001 0x00010101>; |
| 72 | bootph-all; |
| 73 | }; |
| 74 | }; |
| 75 | |
| 76 | To call the nodes use: |
| 77 | |
| 78 | ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg0", &dev); |
| 79 | ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg1", &dev); |
| 80 | |