dts/upstream/Bindings/clock/rockchip,rk3568-cru.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ROCKCHIP rk3568 Family Clock Control Module

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3568 clock controller generates the clock and also implements a
  reset controller for SoC peripherals.
  (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
  used in device tree sources.

properties:
  compatible:
    enum:
      - rockchip,rk3568-cru
      - rockchip,rk3568-pmucru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    pmucru: clock-controller@fdd00000 {
      compatible = "rockchip,rk3568-pmucru";
      reg = <0xfdd00000 0x1000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };
  - |
    cru: clock-controller@fdd20000 {
      compatible = "rockchip,rk3568-cru";
      reg = <0xfdd20000 0x1000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };