Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 00bb187e5e7c6c920ae4979b8431a3544853f775 / . / board / freescale / mx7ulp_evk / plugin.S
blob: 9eab36520a5b319ebf65ced107bf04b8b95c237d [file] [log] [blame]
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]1/*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <config.h>
8
9.macro imx7ulp_ddr_freq_decrease
10 ldr r2, =0x403f0000
11 ldr r3, =0x00000000
12 str r3, [r2, #0xdc]
13
14 ldr r2, =0x403e0000
15 ldr r3, =0x01000020
16 str r3, [r2, #0x40]
17 ldr r3, =0x01000000
18 str r3, [r2, #0x500]
19 ldr r3, =0x80808080
20 str r3, [r2, #0x50c]
21 ldr r3, =0x00140000
22 str r3, [r2, #0x508]
23 ldr r3, =0x00000004
24 str r3, [r2, #0x510]
25 ldr r3, =0x00000002
26 str r3, [r2, #0x514]
27 ldr r3, =0x00000001
28 str r3, [r2, #0x500]
29
30 ldr r3, =0x01000000
31wait1:
32 ldr r4, [r2, #0x500]
33 and r4, r3
34 cmp r4, r3
35 bne wait1
36
37 ldr r3, =0x8080801E
38 str r3, [r2, #0x50c]
39
40 ldr r3, =0x00000040
41wait2:
42 ldr r4, [r2, #0x50c]
43 and r4, r3
44 cmp r4, r3
45 bne wait2
46
47 ldr r3, =0x00000001
48 str r3, [r2, #0x30]
49 ldr r3, =0x11000020
50 str r3, [r2, #0x40]
51
52 ldr r2, =0x403f0000
53 ldr r3, =0x42000000
54 str r3, [r2, #0xdc]
55
56.endm
57
58.macro imx7ulp_evk_ddr_setting
59
60 imx7ulp_ddr_freq_decrease
61
62 /* Enable MMDC PCC clock */
63 ldr r2, =0x40b30000
64 ldr r3, =0x40000000
65 str r3, [r2, #0xac]
66
67 /* Configure DDR pad */
68 ldr r0, =0x40ad0000
69 ldr r1, =0x00040000
70 str r1, [r0, #0x128]
71 ldr r1, =0x0
72 str r1, [r0, #0xf8]
73 ldr r1, =0x00000180
74 str r1, [r0, #0xd8]
75 ldr r1, =0x00000180
76 str r1, [r0, #0x108]
77 ldr r1, =0x00000180
78 str r1, [r0, #0x104]
79 ldr r1, =0x00010000
80 str r1, [r0, #0x124]
81 ldr r1, =0x0000018C
82 str r1, [r0, #0x80]
83 ldr r1, =0x0000018C
84 str r1, [r0, #0x84]
85 ldr r1, =0x0000018C
86 str r1, [r0, #0x88]
87 ldr r1, =0x0000018C
88 str r1, [r0, #0x8c]
89
90 ldr r1, =0x00010000
91 str r1, [r0, #0x120]
92 ldr r1, =0x00000180
93 str r1, [r0, #0x10c]
94 ldr r1, =0x00000180
95 str r1, [r0, #0x110]
96 ldr r1, =0x00000180
97 str r1, [r0, #0x114]
98 ldr r1, =0x00000180
99 str r1, [r0, #0x118]
100 ldr r1, =0x00000180
101 str r1, [r0, #0x90]
102 ldr r1, =0x00000180
103 str r1, [r0, #0x94]
104 ldr r1, =0x00000180
105 str r1, [r0, #0x98]
106 ldr r1, =0x00000180
107 str r1, [r0, #0x9c]
108 ldr r1, =0x00040000
109 str r1, [r0, #0xe0]
110 ldr r1, =0x00040000
111 str r1, [r0, #0xe4]
112
113 ldr r0, =0x40ab0000
114 ldr r1, =0x00008000
115 str r1, [r0, #0x1c]
116 ldr r1, =0xA1390003
117 str r1, [r0, #0x800]
118 ldr r1, =0x0D3900A0
119 str r1, [r0, #0x85c]
120 ldr r1, =0x00400000
121 str r1, [r0, #0x890]
122
123 ldr r1, =0x40404040
124 str r1, [r0, #0x848]
125 ldr r1, =0x40404040
126 str r1, [r0, #0x850]
127 ldr r1, =0x33333333
128 str r1, [r0, #0x81c]
129 ldr r1, =0x33333333
130 str r1, [r0, #0x820]
131 ldr r1, =0x33333333
132 str r1, [r0, #0x824]
133 ldr r1, =0x33333333
134 str r1, [r0, #0x828]
135
136 ldr r1, =0xf3333333
137 str r1, [r0, #0x82c]
138 ldr r1, =0xf3333333
139 str r1, [r0, #0x830]
140 ldr r1, =0xf3333333
141 str r1, [r0, #0x834]
142 ldr r1, =0xf3333333
143 str r1, [r0, #0x838]
144
145 ldr r1, =0x24922492
146 str r1, [r0, #0x8c0]
147 ldr r1, =0x00000800
148 str r1, [r0, #0x8b8]
149
150 ldr r1, =0x00020052
151 str r1, [r0, #0x4]
152 ldr r1, =0x292C42F3
153 str r1, [r0, #0xc]
154 ldr r1, =0x00100A22
155 str r1, [r0, #0x10]
156 ldr r1, =0x00120556
157 str r1, [r0, #0x38]
158 ldr r1, =0x00C700DB
159 str r1, [r0, #0x14]
160 ldr r1, =0x00211718
161 str r1, [r0, #0x18]
162
163 ldr r1, =0x0F9F26D2
164 str r1, [r0, #0x2c]
165 ldr r1, =0x009F0E10
166 str r1, [r0, #0x30]
167 ldr r1, =0x0000003F
168 str r1, [r0, #0x40]
169 ldr r1, =0xC3190000
170 str r1, [r0, #0x0]
171
172 ldr r1, =0x00008050
173 str r1, [r0, #0x1c]
174 ldr r1, =0x00008058
175 str r1, [r0, #0x1c]
176 ldr r1, =0x003F8030
177 str r1, [r0, #0x1c]
178 ldr r1, =0x003F8038
179 str r1, [r0, #0x1c]
180 ldr r1, =0xFF0A8030
181 str r1, [r0, #0x1c]
182 ldr r1, =0xFF0A8038
183 str r1, [r0, #0x1c]
184 ldr r1, =0x04028030
185 str r1, [r0, #0x1c]
186 ldr r1, =0x04028038
187 str r1, [r0, #0x1c]
188 ldr r1, =0x83018030
189 str r1, [r0, #0x1c]
190 ldr r1, =0x83018038
191 str r1, [r0, #0x1c]
192 ldr r1, =0x01038030
193 str r1, [r0, #0x1c]
194 ldr r1, =0x01038038
195 str r1, [r0, #0x1c]
196
197 ldr r1, =0x20000000
198 str r1, [r0, #0x83c]
199
200 ldr r1, =0x00001800
201 str r1, [r0, #0x20]
202 ldr r1, =0xA1310000
203 str r1, [r0, #0x800]
204 ldr r1, =0x00020052
205 str r1, [r0, #0x4]
206 ldr r1, =0x00011006
207 str r1, [r0, #0x404]
208 ldr r1, =0x00000000
209 str r1, [r0, #0x1c]
210
211.endm
212
213.macro imx7ulp_clock_gating
214.endm
215
216.macro imx7ulp_qos_setting
217.endm
218
219.macro imx7ulp_ddr_setting
220 imx7ulp_evk_ddr_setting
221.endm
222
223/* include the common plugin code here */
224#include <asm/arch/mx7ulp_plugin.S>