blob: cb6285a8d1285fb95cb004fa19a48ddfe8df35dd [file] [log] [blame]
Jernej Skrabec415ef9b2021-01-11 21:11:50 +01001/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2/*
3 * Copyright (C) 2020 Arm Ltd.
4 */
5
6#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_
7#define _DT_BINDINGS_RESET_SUN50I_H616_H_
8
9#define RST_MBUS 0
10#define RST_BUS_DE 1
11#define RST_BUS_DEINTERLACE 2
12#define RST_BUS_GPU 3
13#define RST_BUS_CE 4
14#define RST_BUS_VE 5
15#define RST_BUS_DMA 6
16#define RST_BUS_HSTIMER 7
17#define RST_BUS_DBG 8
18#define RST_BUS_PSI 9
19#define RST_BUS_PWM 10
20#define RST_BUS_IOMMU 11
21#define RST_BUS_DRAM 12
22#define RST_BUS_NAND 13
23#define RST_BUS_MMC0 14
24#define RST_BUS_MMC1 15
25#define RST_BUS_MMC2 16
26#define RST_BUS_UART0 17
27#define RST_BUS_UART1 18
28#define RST_BUS_UART2 19
29#define RST_BUS_UART3 20
30#define RST_BUS_UART4 21
31#define RST_BUS_UART5 22
32#define RST_BUS_I2C0 23
33#define RST_BUS_I2C1 24
34#define RST_BUS_I2C2 25
35#define RST_BUS_I2C3 26
36#define RST_BUS_I2C4 27
37#define RST_BUS_SPI0 28
38#define RST_BUS_SPI1 29
39#define RST_BUS_EMAC0 30
40#define RST_BUS_EMAC1 31
41#define RST_BUS_TS 32
42#define RST_BUS_THS 33
43#define RST_BUS_SPDIF 34
44#define RST_BUS_DMIC 35
45#define RST_BUS_AUDIO_CODEC 36
46#define RST_BUS_AUDIO_HUB 37
47#define RST_USB_PHY0 38
48#define RST_USB_PHY1 39
49#define RST_USB_PHY2 40
50#define RST_USB_PHY3 41
51#define RST_BUS_OHCI0 42
52#define RST_BUS_OHCI1 43
53#define RST_BUS_OHCI2 44
54#define RST_BUS_OHCI3 45
55#define RST_BUS_EHCI0 46
56#define RST_BUS_EHCI1 47
57#define RST_BUS_EHCI2 48
58#define RST_BUS_EHCI3 49
59#define RST_BUS_OTG 50
60#define RST_BUS_HDMI 51
61#define RST_BUS_HDMI_SUB 52
62#define RST_BUS_TCON_TOP 53
63#define RST_BUS_TCON_TV0 54
64#define RST_BUS_TCON_TV1 55
65#define RST_BUS_TVE_TOP 56
66#define RST_BUS_TVE0 57
67#define RST_BUS_HDCP 58
68#define RST_BUS_KEYADC 59
69
70#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */