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git01.mediatek.com / filogic / uboot / 00ad1f0f857a901b20dd91a3415d1e71bb75a66a / . / configs / socfpga_mcvevk_defconfig
blob: 455ea958e7e536466944d3f402bc43c27dca224a [file] [log] [blame]
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_SOCFPGA=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_SPL_DM=y
5CONFIG_DM_GPIO=y
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]6CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]7CONFIG_SPL_STACK_R_ADDR=0x00800000
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
9CONFIG_SPL=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]10CONFIG_SPL_STACK_R=y
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]11# CONFIG_CMD_IMLS is not set
12# CONFIG_CMD_FLASH is not set
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]13CONFIG_CMD_GPIO=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]14CONFIG_SPL_SIMPLE_BUS=y
15CONFIG_DWAPB_GPIO=y
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]16CONFIG_DM_ETH=y
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]17CONFIG_ETH_DESIGNWARE=y