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git01.mediatek.com / filogic / uboot / 00a0b56f93f2fa3dcaac26cd2be3b2a256ce7e2e / . / board / freescale / m5373evb / nand.c
blob: 92cef2a97dbcaca29517f1d2a3e5c0b7f64e8c76 [file] [log] [blame]
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]1/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Alison Wang35d23df2012-03-26 21:49:05 +0000[diff] [blame]5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]9 */
10
11#include <config.h>
12#include <common.h>
13#include <asm/io.h>
14#include <asm/immap.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#if defined(CONFIG_CMD_NAND)
19#include <nand.h>
20#include <linux/mtd/mtd.h>
21
22#define SET_CLE 0x10
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]23#define SET_ALE 0x08
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]24
Scott Woodfdda9462008-08-13 17:53:48 -0500[diff] [blame]25static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]26{
27 struct nand_chip *this = mtdinfo->priv;
TsiChung Liew476f6bc2008-10-24 12:59:12 +0000[diff] [blame]28 volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]29
Scott Woodfdda9462008-08-13 17:53:48 -0500[diff] [blame]30 if (ctrl & NAND_CTRL_CHANGE) {
31 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]32
TsiChung Liew476f6bc2008-10-24 12:59:12 +0000[diff] [blame]33 IO_ADDR_W &= ~(SET_ALE | SET_CLE);
TsiChung Liew476f6bc2008-10-24 12:59:12 +0000[diff] [blame]34
35 if (ctrl & NAND_NCE)
TsiChung Liew64979662009-03-02 19:16:45 +0000[diff] [blame]36 *nCE &= 0xFFFB;
37 else
TsiChung Liew476f6bc2008-10-24 12:59:12 +0000[diff] [blame]38 *nCE |= 0x0004;
TsiChung Liew64979662009-03-02 19:16:45 +0000[diff] [blame]39
Scott Woodfdda9462008-08-13 17:53:48 -0500[diff] [blame]40 if (ctrl & NAND_CLE)
41 IO_ADDR_W |= SET_CLE;
42 if (ctrl & NAND_ALE)
43 IO_ADDR_W |= SET_ALE;
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]44
Scott Woodfdda9462008-08-13 17:53:48 -0500[diff] [blame]45 this->IO_ADDR_W = (void *)IO_ADDR_W;
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]46
Scott Woodfdda9462008-08-13 17:53:48 -0500[diff] [blame]47 }
48
49 if (cmd != NAND_CMD_NONE)
50 writeb(cmd, this->IO_ADDR_W);
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]51}
52
53int board_nand_init(struct nand_chip *nand)
54{
Alison Wang35d23df2012-03-26 21:49:05 +0000[diff] [blame]55 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
56 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]57
Alison Wang35d23df2012-03-26 21:49:05 +0000[diff] [blame]58 clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]59
TsiChung Liew476f6bc2008-10-24 12:59:12 +0000[diff] [blame]60 /*
61 * set up pin configuration - enabled 2nd output buffer's signals
62 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
63 * to use nCE signal
64 */
Alison Wang35d23df2012-03-26 21:49:05 +0000[diff] [blame]65 clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
66 setbits_8(&gpio->pddr_timer, 0x08);
67 setbits_8(&gpio->ppd_timer, 0x08);
68 out_8(&gpio->pclrr_timer, 0);
69 out_8(&gpio->podr_timer, 0);
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]70
TsiChung Liew64979662009-03-02 19:16:45 +0000[diff] [blame]71 nand->chip_delay = 60;
Scott Woodfdda9462008-08-13 17:53:48 -0500[diff] [blame]72 nand->ecc.mode = NAND_ECC_SOFT;
73 nand->cmd_ctrl = nand_hwcontrol;
TsiChungLiewf7d060c2008-01-14 17:19:54 -0600[diff] [blame]74
75 return 0;
76}
77#endif