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git01.mediatek.com / filogic / uboot / 009afd3bbf2416fedd4e31556a0d952e2ace6f91 / . / include / configs / socfpga_cyclone5.h
blob: c3d958cb3077ddf1211c8aa57efd46edfcbfaf94 [file] [log] [blame]
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]1/*
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]2 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]5 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]6#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
7#define __CONFIG_SOCFPGA_CYCLONE5_H__
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]8
9#include <asm/arch/socfpga_base_addrs.h>
Chin Liang See70fa4e72013-09-11 11:24:48 -0500[diff] [blame]10#include "../../board/altera/socfpga/pinmux_config.h"
Chin Liang See63550242014-06-10 01:17:42 -0500[diff] [blame]11#include "../../board/altera/socfpga/iocsr_config.h"
Chin Liang Seecb350602014-03-04 22:13:53 -0600[diff] [blame]12#include "../../board/altera/socfpga/pll_config.h"
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]13
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]14/* U-Boot Commands */
15#define CONFIG_SYS_NO_FLASH
16#include <config_cmd_default.h>
17#define CONFIG_DOS_PARTITION
18#define CONFIG_FAT_WRITE
19#define CONFIG_HW_WATCHDOG
Marek Vasutbd279e32014-09-15 01:27:57 +0200[diff] [blame]20
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]21#define CONFIG_CMD_ASKENV
22#define CONFIG_CMD_BOOTZ
23#define CONFIG_CMD_CACHE
24#define CONFIG_CMD_DHCP
25#define CONFIG_CMD_EXT4
26#define CONFIG_CMD_EXT4_WRITE
27#define CONFIG_CMD_FAT
28#define CONFIG_CMD_FPGA
Marek Vasut08c71a62014-09-19 13:28:47 +0200[diff] [blame]29#define CONFIG_CMD_FS_GENERIC
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]30#define CONFIG_CMD_GREPENV
31#define CONFIG_CMD_MII
32#define CONFIG_CMD_MMC
33#define CONFIG_CMD_NET
34#define CONFIG_CMD_PING
35#define CONFIG_CMD_SETEXPR
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]36
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]37#define CONFIG_REGEX /* Enable regular expression support */
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]38
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]39/* Memory configurations */
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]40#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]41
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]42/* Booting Linux */
43#define CONFIG_BOOTDELAY 3
44#define CONFIG_BOOTFILE "zImage"
Anatolij Gustschinb02c7982014-11-07 01:12:03 +0100[diff] [blame]45#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
Chin Liang See4a6a2282014-09-19 05:33:19 -0500[diff] [blame]46#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]47#define CONFIG_BOOTCOMMAND "run ramboot"
Chin Liang See4a6a2282014-09-19 05:33:19 -0500[diff] [blame]48#else
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]49#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
Chin Liang See4a6a2282014-09-19 05:33:19 -0500[diff] [blame]50#endif
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]51#define CONFIG_LOADADDR 0x8000
52#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]53
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]54/* Ethernet on SoC (EMAC) */
55#if defined(CONFIG_CMD_NET)
Marek Vasut3835fbe2014-10-10 01:50:23 +0200[diff] [blame]56#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]57#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]58
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]59/* PHY */
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]60#define CONFIG_PHY_MICREL
61#define CONFIG_PHY_MICREL_KSZ9021
62#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
63#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
64#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
65#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
66
Chin Liang See9cd12042013-08-07 10:06:56 -0500[diff] [blame]67#endif
Pavel Machekce340e92014-07-14 14:14:17 +0200[diff] [blame]68
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]69/* Extra Environment */
70#define CONFIG_HOSTNAME socfpga_cyclone5
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]71
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]72#define CONFIG_EXTRA_ENV_SETTINGS \
73 "verify=n\0" \
74 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
75 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
76 "bootm ${loadaddr} - ${fdt_addr}\0" \
77 "bootimage=zImage\0" \
78 "fdt_addr=100\0" \
79 "fdtimage=socfpga.dtb\0" \
80 "fsloadcmd=ext2load\0" \
81 "bootm ${loadaddr} - ${fdt_addr}\0" \
82 "mmcroot=/dev/mmcblk0p2\0" \
83 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
84 " root=${mmcroot} rw rootwait;" \
85 "bootz ${loadaddr} - ${fdt_addr}\0" \
86 "mmcload=mmc rescan;" \
Marek Vasut08c71a62014-09-19 13:28:47 +0200[diff] [blame]87 "load mmc 0:1 ${loadaddr} ${bootimage};" \
88 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]89 "qspiroot=/dev/mtdblock0\0" \
90 "qspirootfstype=jffs2\0" \
91 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
92 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
93 "bootm ${loadaddr} - ${fdt_addr}\0"
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]94
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]95/* The rest of the configuration is shared */
96#include <configs/socfpga_common.h>
Chin Liang See561c9d42014-06-10 01:11:04 -0500[diff] [blame]97
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]98#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */