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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Haiying Wangbd255372009-03-27 17:02:45 -04002/*
Kumar Gala6ad0eb52011-01-04 18:04:01 -06003 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Haiying Wangbd255372009-03-27 17:02:45 -04004 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Haiying Wangbd255372009-03-27 17:02:45 -04007 */
8
9#include <common.h>
10#include <asm/fsl_law.h>
11#include <asm/mmu.h>
12
13/*
14 * LAW(Local Access Window) configuration:
15 *
16 *0) 0x0000_0000 0x7fff_ffff DDR 2G
17 *1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
18 *-) 0xe000_0000 0xe00f_ffff CCSR 1M
19 *2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
20 *3) 0xc000_0000 0xdfff_ffff SRIO 512MB
21 *4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
22 *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
23 *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
24 *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
25 *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
26 *
27 *Notes:
28 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
29 * If flash is 8M at default position (last 8M), no LAW needed.
30 *
31 */
32
33struct law_entry law_table[] = {
34#ifndef CONFIG_SPD_EEPROM
35 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
36#endif
Haiying Wangbd255372009-03-27 17:02:45 -040037 SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
Haiying Wangbd255372009-03-27 17:02:45 -040038};
39
40int num_law_entries = ARRAY_SIZE(law_table);