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git01.mediatek.com / filogic / uboot / 008a1ec8e8900da2da3d88f6c06318f7ffb16d5a / . / arch / arm / cpu / armv7 / exynos / clock_init.h
blob: c28ff3ab14f52bfe0cb44f100053d79ebef1c97a [file] [log] [blame]
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]1/*
2 * Clock initialization routines
3 *
4 * Copyright (c) 2011 The Chromium OS Authors.
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]7 */
8
9#ifndef __EXYNOS_CLOCK_INIT_H
10#define __EXYNOS_CLOCK_INIT_H
11
12enum {
13 MEM_TIMINGS_MSR_COUNT = 4,
14};
15
16/* These are the ratio's for configuring ARM clock */
17struct arm_clk_ratios {
18 unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
19
20 unsigned apll_mdiv;
21 unsigned apll_pdiv;
22 unsigned apll_sdiv;
23
24 unsigned arm2_ratio;
25 unsigned apll_ratio;
26 unsigned pclk_dbg_ratio;
27 unsigned atb_ratio;
28 unsigned periph_ratio;
29 unsigned acp_ratio;
30 unsigned cpud_ratio;
31 unsigned arm_ratio;
32};
33
34/* These are the memory timings for a particular memory type and speed */
35struct mem_timings {
36 enum mem_manuf mem_manuf; /* Memory manufacturer */
37 enum ddr_mode mem_type; /* Memory type */
38 unsigned frequency_mhz; /* Frequency of memory in MHz */
39
40 /* Here follow the timing parameters for the selected memory */
41 unsigned apll_mdiv;
42 unsigned apll_pdiv;
43 unsigned apll_sdiv;
44 unsigned mpll_mdiv;
45 unsigned mpll_pdiv;
46 unsigned mpll_sdiv;
47 unsigned cpll_mdiv;
48 unsigned cpll_pdiv;
49 unsigned cpll_sdiv;
50 unsigned gpll_mdiv;
51 unsigned gpll_pdiv;
52 unsigned gpll_sdiv;
53 unsigned epll_mdiv;
54 unsigned epll_pdiv;
55 unsigned epll_sdiv;
56 unsigned vpll_mdiv;
57 unsigned vpll_pdiv;
58 unsigned vpll_sdiv;
59 unsigned bpll_mdiv;
60 unsigned bpll_pdiv;
61 unsigned bpll_sdiv;
62 unsigned pclk_cdrex_ratio;
63 unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
64
65 unsigned timing_ref;
66 unsigned timing_row;
67 unsigned timing_data;
68 unsigned timing_power;
69
70 /* DQS, DQ, DEBUG offsets */
71 unsigned phy0_dqs;
72 unsigned phy1_dqs;
73 unsigned phy0_dq;
74 unsigned phy1_dq;
75 unsigned phy0_tFS;
76 unsigned phy1_tFS;
77 unsigned phy0_pulld_dqs;
78 unsigned phy1_pulld_dqs;
79
80 unsigned lpddr3_ctrl_phy_reset;
81 unsigned ctrl_start_point;
82 unsigned ctrl_inc;
83 unsigned ctrl_start;
84 unsigned ctrl_dll_on;
85 unsigned ctrl_ref;
86
87 unsigned ctrl_force;
88 unsigned ctrl_rdlat;
89 unsigned ctrl_bstlen;
90
91 unsigned fp_resync;
92 unsigned iv_size;
93 unsigned dfi_init_start;
94 unsigned aref_en;
95
96 unsigned rd_fetch;
97
98 unsigned zq_mode_dds;
99 unsigned zq_mode_term;
100 unsigned zq_mode_noterm; /* 1 to allow termination disable */
101
102 unsigned memcontrol;
103 unsigned memconfig;
104
105 unsigned membaseconfig0;
106 unsigned membaseconfig1;
107 unsigned prechconfig_tp_cnt;
108 unsigned dpwrdn_cyc;
109 unsigned dsref_cyc;
110 unsigned concontrol;
111 /* Channel and Chip Selection */
112 uint8_t dmc_channels; /* number of memory channels */
113 uint8_t chips_per_channel; /* number of chips per channel */
114 uint8_t chips_to_configure; /* number of chips to configure */
115 uint8_t send_zq_init; /* 1 to send this command */
116 unsigned impedance; /* drive strength impedeance */
117 uint8_t gate_leveling_enable; /* check gate leveling is enabled */
118};
119
120/**
121 * Get the correct memory timings for our selected memory type and speed.
122 *
123 * This function can be called from SPL or the main U-Boot.
124 *
125 * @return pointer to the memory timings that we should use
126 */
127struct mem_timings *clock_get_mem_timings(void);
128
129/*
130 * Initialize clock for the device
131 */
132void system_clock_init(void);
Amare33add82013-04-27 11:42:59 +0530[diff] [blame]133
134/*
135 * Set clock divisor value for booting from EMMC.
136 */
137void emmc_boot_clk_div_set(void);
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]138#endif