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git01.mediatek.com / filogic / uboot / 0089b8795f227912ee61d0e7d7296805e1c8f968 / . / board / prodrive / alpr / init.S
blob: 119bc534e7b8f9916bb9656a4b102cf95de43fe1 [file] [log] [blame]
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]1/*
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]23
24#include <ppc_asm.tmpl>
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]25#include <asm/mmu.h>
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]26#include <config.h>
Stefan Roese3ddce572010-09-20 16:05:31 +0200[diff] [blame]27#include <asm/ppc4xx.h>
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]28
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]29/**************************************************************************
30 * TLB TABLE
31 *
32 * This table is used by the cpu boot code to setup the initial tlb
33 * entries. Rather than make broad assumptions in the cpu source tree,
34 * this table lets each board set things up however they like.
35 *
36 * Pointer to the table is returned in r1
37 *
38 *************************************************************************/
39
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]40 .section .bootpg,"ax"
41 .globl tlbtab
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]42
43tlbtab:
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]44 tlbtab_start
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]45 tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
46 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
47 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
48 tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]49#ifdef CONFIG_4xx_DCACHE
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]50 tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]51#else
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]52 tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]53#endif
54
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]55#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]56 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]57 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]58#endif
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]59 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]60
61 /* PCI */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]62 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
63 tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
64 tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]65
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]66 /* NAND */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]67 tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]68 tlbtab_end