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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Aneesh V686a0752011-06-16 23:30:51 +00002/*
3 * (C) Copyright 2010
4 * Texas Instruments, <www.ti.com>
5 * Aneesh V <aneesh@ti.com>
Aneesh V686a0752011-06-16 23:30:51 +00006 */
7#include <linux/types.h>
8#include <asm/io.h>
9#include <asm/armv7.h>
10#include <asm/pl310.h>
11#include <config.h>
Tom Riniabb9a042024-05-18 20:20:43 -060012#include <common.h>
Aneesh V686a0752011-06-16 23:30:51 +000013
Tom Rini6a5dccc2022-11-16 13:10:41 -050014struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
Aneesh V686a0752011-06-16 23:30:51 +000015
16static void pl310_cache_sync(void)
17{
18 writel(0, &pl310->pl310_cache_sync);
19}
20
21static void pl310_background_op_all_ways(u32 *op_reg)
22{
23 u32 assoc_16, associativity, way_mask;
24
25 assoc_16 = readl(&pl310->pl310_aux_ctrl) &
26 PL310_AUX_CTRL_ASSOCIATIVITY_MASK;
27 if (assoc_16)
28 associativity = 16;
29 else
30 associativity = 8;
31
32 way_mask = (1 << associativity) - 1;
33 /* Invalidate all ways */
34 writel(way_mask, op_reg);
35 /* Wait for all ways to be invalidated */
Marek Vasut8791b1f2019-02-19 01:43:51 +010036 while (readl(op_reg) & way_mask)
Aneesh V686a0752011-06-16 23:30:51 +000037 ;
38 pl310_cache_sync();
39}
40
41void v7_outer_cache_inval_all(void)
42{
43 pl310_background_op_all_ways(&pl310->pl310_inv_way);
44}
45
46void v7_outer_cache_flush_all(void)
47{
48 pl310_background_op_all_ways(&pl310->pl310_clean_inv_way);
49}
50
51/* Flush(clean invalidate) memory from start to stop-1 */
52void v7_outer_cache_flush_range(u32 start, u32 stop)
53{
54 /* PL310 currently supports only 32 bytes cache line */
55 u32 pa, line_size = 32;
56
57 /*
58 * Align to the beginning of cache-line - this ensures that
59 * the first 5 bits are 0 as required by PL310 TRM
60 */
61 start &= ~(line_size - 1);
62
63 for (pa = start; pa < stop; pa = pa + line_size)
64 writel(pa, &pl310->pl310_clean_inv_line_pa);
65
66 pl310_cache_sync();
67}
68
69/* invalidate memory from start to stop-1 */
70void v7_outer_cache_inval_range(u32 start, u32 stop)
71{
72 /* PL310 currently supports only 32 bytes cache line */
73 u32 pa, line_size = 32;
74
75 /*
Aneesh V6a22a622011-08-11 04:35:45 +000076 * If start address is not aligned to cache-line do not
77 * invalidate the first cache-line
Aneesh V686a0752011-06-16 23:30:51 +000078 */
79 if (start & (line_size - 1)) {
Aneesh V6a22a622011-08-11 04:35:45 +000080 printf("ERROR: %s - start address is not aligned - 0x%08x\n",
81 __func__, start);
Aneesh V686a0752011-06-16 23:30:51 +000082 /* move to next cache line */
83 start = (start + line_size - 1) & ~(line_size - 1);
84 }
85
86 /*
Aneesh V6a22a622011-08-11 04:35:45 +000087 * If stop address is not aligned to cache-line do not
88 * invalidate the last cache-line
Aneesh V686a0752011-06-16 23:30:51 +000089 */
90 if (stop & (line_size - 1)) {
Aneesh V6a22a622011-08-11 04:35:45 +000091 printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
92 __func__, stop);
Aneesh V686a0752011-06-16 23:30:51 +000093 /* align to the beginning of this cache line */
94 stop &= ~(line_size - 1);
95 }
96
97 for (pa = start; pa < stop; pa = pa + line_size)
98 writel(pa, &pl310->pl310_inv_line_pa);
99
100 pl310_cache_sync();
101}