Paul Barker | a27d9f6 | 2021-07-12 21:14:09 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
| 4 | */ |
| 5 | |
| 6 | #include <dt-bindings/display/tda998x.h> |
| 7 | #include <dt-bindings/interrupt-controller/irq.h> |
| 8 | |
| 9 | &ldo3_reg { |
| 10 | regulator-min-microvolt = <1800000>; |
| 11 | regulator-max-microvolt = <1800000>; |
| 12 | regulator-always-on; |
| 13 | }; |
| 14 | |
| 15 | &mmc1 { |
| 16 | vmmc-supply = <&vmmcsd_fixed>; |
| 17 | }; |
| 18 | |
| 19 | &mmc2 { |
| 20 | vmmc-supply = <&vmmcsd_fixed>; |
| 21 | pinctrl-names = "default"; |
| 22 | pinctrl-0 = <&emmc_pins>; |
| 23 | bus-width = <8>; |
| 24 | status = "okay"; |
| 25 | non-removable; |
| 26 | }; |
| 27 | |
| 28 | &am33xx_pinmux { |
| 29 | nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { |
| 30 | pinctrl-single,pins = < |
| 31 | AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) |
| 32 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) |
| 33 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) |
| 34 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) |
| 35 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) |
| 36 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) |
| 37 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) |
| 38 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) |
| 39 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) |
| 40 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) |
| 41 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) |
| 42 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) |
| 43 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) |
| 44 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) |
| 45 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) |
| 46 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) |
| 47 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) |
| 48 | AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 49 | AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 50 | AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 51 | AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 52 | >; |
| 53 | }; |
| 54 | |
| 55 | nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { |
| 56 | pinctrl-single,pins = < |
| 57 | AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) |
| 58 | >; |
| 59 | }; |
| 60 | |
| 61 | mcasp0_pins: mcasp0_pins { |
| 62 | pinctrl-single,pins = < |
| 63 | AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ |
| 64 | AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ |
| 65 | AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) |
| 66 | AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 67 | AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ |
| 68 | >; |
| 69 | }; |
| 70 | }; |
| 71 | |
| 72 | &lcdc { |
| 73 | status = "okay"; |
| 74 | |
| 75 | /* If you want to get 24 bit RGB and 16 BGR mode instead of |
| 76 | * current 16 bit RGB and 24 BGR modes, set the propety |
| 77 | * below to "crossed" and uncomment the video-ports -property |
| 78 | * in tda19988 node. |
| 79 | */ |
| 80 | blue-and-red-wiring = "straight"; |
| 81 | |
| 82 | port { |
| 83 | lcdc_0: endpoint@0 { |
| 84 | remote-endpoint = <&hdmi_0>; |
| 85 | }; |
| 86 | }; |
| 87 | }; |
| 88 | |
| 89 | &i2c0 { |
| 90 | tda19988: tda19988@70 { |
| 91 | compatible = "nxp,tda998x"; |
| 92 | reg = <0x70>; |
| 93 | nxp,calib-gpios = <&gpio1 25 0>; |
| 94 | interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; |
| 95 | |
| 96 | pinctrl-names = "default", "off"; |
| 97 | pinctrl-0 = <&nxp_hdmi_bonelt_pins>; |
| 98 | pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; |
| 99 | |
| 100 | /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ |
| 101 | /* video-ports = <0x234501>; */ |
| 102 | |
| 103 | #sound-dai-cells = <0>; |
| 104 | audio-ports = < TDA998x_I2S 0x03>; |
| 105 | |
| 106 | ports { |
| 107 | port@0 { |
| 108 | hdmi_0: endpoint@0 { |
| 109 | remote-endpoint = <&lcdc_0>; |
| 110 | }; |
| 111 | }; |
| 112 | }; |
| 113 | }; |
| 114 | }; |
| 115 | |
| 116 | &rtc { |
| 117 | system-power-controller; |
| 118 | }; |
| 119 | |
| 120 | &mcasp0 { |
| 121 | #sound-dai-cells = <0>; |
| 122 | pinctrl-names = "default"; |
| 123 | pinctrl-0 = <&mcasp0_pins>; |
| 124 | status = "okay"; |
| 125 | op-mode = <0>; /* MCASP_IIS_MODE */ |
| 126 | tdm-slots = <2>; |
| 127 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 128 | 0 0 1 0 |
| 129 | >; |
| 130 | tx-num-evt = <32>; |
| 131 | rx-num-evt = <32>; |
| 132 | }; |
| 133 | |
| 134 | / { |
| 135 | memory@80000000 { |
| 136 | device_type = "memory"; |
| 137 | reg = <0x80000000 0x20000000>; /* 512 MB */ |
| 138 | }; |
| 139 | |
| 140 | clk_mcasp0_fixed: clk_mcasp0_fixed { |
| 141 | #clock-cells = <0>; |
| 142 | compatible = "fixed-clock"; |
| 143 | clock-frequency = <24576000>; |
| 144 | }; |
| 145 | |
| 146 | clk_mcasp0: clk_mcasp0 { |
| 147 | #clock-cells = <0>; |
| 148 | compatible = "gpio-gate-clock"; |
| 149 | clocks = <&clk_mcasp0_fixed>; |
| 150 | enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ |
| 151 | }; |
| 152 | |
| 153 | sound { |
| 154 | compatible = "simple-audio-card"; |
| 155 | simple-audio-card,name = "TI BeagleBone Black"; |
| 156 | simple-audio-card,format = "i2s"; |
| 157 | simple-audio-card,bitclock-master = <&dailink0_master>; |
| 158 | simple-audio-card,frame-master = <&dailink0_master>; |
| 159 | |
| 160 | dailink0_master: simple-audio-card,cpu { |
| 161 | sound-dai = <&mcasp0>; |
| 162 | clocks = <&clk_mcasp0>; |
| 163 | }; |
| 164 | |
| 165 | simple-audio-card,codec { |
| 166 | sound-dai = <&tda19988>; |
| 167 | }; |
| 168 | }; |
| 169 | }; |