blob: 9024364a57f2b19f11894c8714f72713482bb009 [file] [log] [blame]
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +01001/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef __ASM_MACH_MSCC_IOREMAP_H
7#define __ASM_MACH_MSCC_IOREMAP_H
8
9#include <linux/types.h>
10#include <mach/common.h>
11
12/*
13 * Allow physical addresses to be fixed up to help peripherals located
14 * outside the low 32-bit range -- generic pass-through version.
15 */
16static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
17 phys_addr_t size)
18{
19 return phys_addr;
20}
21
22static inline int is_vcoreiii_internal_registers(phys_addr_t offset)
23{
24 if ((offset >= MSCC_IO_ORIGIN1_OFFSET &&
25 offset < (MSCC_IO_ORIGIN1_OFFSET + MSCC_IO_ORIGIN1_SIZE)) ||
26 (offset >= MSCC_IO_ORIGIN2_OFFSET &&
27 offset < (MSCC_IO_ORIGIN2_OFFSET + MSCC_IO_ORIGIN2_SIZE)))
28 return 1;
29
30 return 0;
31}
32
33static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
34 unsigned long flags)
35{
36 if (is_vcoreiii_internal_registers(offset))
37 return (void __iomem *)offset;
38
39 return NULL;
40}
41
42static inline int plat_iounmap(const volatile void __iomem *addr)
43{
44 return is_vcoreiii_internal_registers((unsigned long)addr);
45}
46
47#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
48
49#endif /* __ASM_MACH_MSCC_IOREMAP_H */