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git01.mediatek.com / filogic / uboot / 000bb0bc55a07fe52575ed6e542044b57a333944 / . / arch / arm / dts / zynqmp-sc-vpk180-revB.dtso
blob: 3990d053c351f4858fdfdc8551fdd4bad67e9496 [file] [log] [blame]
Michal Simekeaa6f3d2023-09-27 11:53:34 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VPK180 revA
4 *
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12
13/dts-v1/;
14/plugin/;
15
Michal Simekeaa6f3d2023-09-27 11:53:34 +0200[diff] [blame]16&{/} {
17 compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB",
18 "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
19
20 vc7_xin: vc7-xin {
21 compatible = "fixed-clock";
22 #clock-cells = <0x0>;
23 clock-frequency = <50000000>;
24 };
25};
26
27&i2c0 {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 tca6416_u233: gpio@20 { /* u233 */
32 compatible = "ti,tca6416";
33 reg = <0x20>;
34 gpio-controller; /* interrupt not connected */
35 #gpio-cells = <2>;
36 gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
37 "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
38 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
39 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
40 };
41
42 i2c-mux@74 { /* u33 */
43 compatible = "nxp,pca9548";
44 #address-cells = <1>;
45 #size-cells = <0>;
46 reg = <0x74>;
47 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
48 pmbus_i2c: i2c@0 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 reg = <0>;
52 /* On connector J325 */
53 ir38060_41: regulator@41 { /* IR38060 - u259 */
54 compatible = "infineon,ir38060", "infineon,ir38064";
55 reg = <0x41>; /* i2c addr 0x11 */
56 };
57 ir35221_45: pmic@45 { /* IR35221 - u291 */
58 compatible = "infineon,ir35221";
59 reg = <0x45>; /* i2c addr - 0x15 */
60 };
61 ir35221_46: pmic@46 { /* IR35221 - u152 */
62 compatible = "infineon,ir35221";
63 reg = <0x46>; /* i2c addr - 0x16 */
64 };
65 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
66 compatible = "infineon,irps5401";
67 reg = <0x47>; /* i2c addr 0x17 */
68 };
69 irps5401_48: pmic@48 { /* IRPS5401 - u295 */
70 compatible = "infineon,irps5401";
71 reg = <0x48>; /* i2c addr 0x18 */
72 };
73 ir38164_49: regulator@49 { /* IR38164 - u189 */
74 compatible = "infineon,ir38164";
75 reg = <0x49>; /* i2c addr 0x19 */
76 };
77 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
78 compatible = "infineon,irps5401";
79 reg = <0x4c>; /* i2c addr 0x1c */
80 };
81 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
82 compatible = "infineon,irps5401";
83 reg = <0x4d>; /* i2c addr 0x1d */
84 };
85 ir38164_4e: regulator@4e { /* IR38164 - u185 */
86 compatible = "infineon,ir38164";
87 reg = <0x4e>; /* i2c addr 0x1e */
88 };
89 ir38164_4f: regulator@4f { /* IR38164 - u187 */
90 compatible = "infineon,ir38164";
91 reg = <0x4f>; /* i2c addr 0x1f */
92 };
93 };
94 pmbus1_ina226_i2c: i2c@1 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 reg = <1>;
98 /* FIXME check alerts coming to SC */
99 vccint: ina226@40 { /* u65 */
100 compatible = "ti,ina226";
101 reg = <0x40>;
102 shunt-resistor = <5000>; /* r440 */
103 };
104 vcc_soc: ina226@41 { /* u161 */
105 compatible = "ti,ina226";
106 reg = <0x41>;
107 shunt-resistor = <5000>; /* r2174 */
108 };
109 vcc_pmc: ina226@42 { /* u163 */
110 compatible = "ti,ina226";
111 reg = <0x42>;
112 shunt-resistor = <5000>; /* r1214 */
113 };
114 vcc_ram: ina226@43 { /* u5 */
115 compatible = "ti,ina226";
116 reg = <0x43>;
117 shunt-resistor = <5000>; /* r2108 */
118 };
119 vcc_pslp: ina226@44 { /* u165 */
120 compatible = "ti,ina226";
121 reg = <0x44>;
122 shunt-resistor = <5000>; /* r1830 */
123 };
124 vcc_psfp: ina226@45 { /* u164 */
125 compatible = "ti,ina226";
126 reg = <0x45>;
127 shunt-resistor = <5000>; /* r2086 */
128 };
129 };
130 i2c@2 { /* NC */ /* FIXME maybe remove */
131 #address-cells = <1>;
132 #size-cells = <0>;
133 reg = <2>;
134 };
135 pmbus2_ina226_i2c: i2c@3 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 reg = <3>;
139 /* FIXME check alerts coming to SC */
140 vccaux: ina226@40 { /* u166 */
141 compatible = "ti,ina226";
142 reg = <0x40>;
143 shunt-resistor = <2000>; /* r2109 */
144 };
145 vccaux_pmc: ina226@41 { /* u168 */
146 compatible = "ti,ina226";
147 reg = <0x41>;
148 shunt-resistor = <5000>; /* r1246 */
149 };
150 mgtavcc: ina226@42 { /* u265 */
151 compatible = "ti,ina226";
152 reg = <0x42>;
153 shunt-resistor = <5000>; /* r1829 */
154 };
155 vcc1v5: ina226@43 { /* u264 */
156 compatible = "ti,ina226";
157 reg = <0x43>;
158 shunt-resistor = <5000>; /* r1221 */
159 };
160 vcco_mio: ina226@45 { /* u172 */
161 compatible = "ti,ina226";
162 reg = <0x45>;
163 shunt-resistor = <5000>; /* r1219 */
164 };
165 mgtavtt: ina226@46 { /* u188 */
166 compatible = "ti,ina226";
167 reg = <0x46>;
168 shunt-resistor = <2000>; /* r1384 */
169 };
170 vcco_502: ina226@47 { /* u174 */
171 compatible = "ti,ina226";
172 reg = <0x47>;
173 shunt-resistor = <5000>; /* r1825 */
174 };
175 mgtvccaux: ina226@48 { /* u176 */
176 compatible = "ti,ina226";
177 reg = <0x48>;
178 shunt-resistor = <5000>; /* r1232 */
179 };
180 vcc1v1_lp4: ina226@49 { /* u186 */
181 compatible = "ti,ina226";
182 reg = <0x49>;
183 shunt-resistor = <2000>; /* r1367 */
184 };
185 vadj_fmc: ina226@4a { /* u184 */
186 compatible = "ti,ina226";
187 reg = <0x4a>;
188 shunt-resistor = <2000>; /* r1350 */
189 };
190 lpdmgtyavcc: ina226@4b { /* u177 */
191 compatible = "ti,ina226";
192 reg = <0x4b>;
193 shunt-resistor = <5000>; /* r2097 */
194 };
195 lpdmgtyavtt: ina226@4c { /* u260 */
196 compatible = "ti,ina226";
197 reg = <0x4c>;
198 shunt-resistor = <2000>; /* r1834 */
199 };
200 lpdmgtyvccaux: ina226@4d { /* u234 */
201 compatible = "ti,ina226";
202 reg = <0x4d>;
203 shunt-resistor = <5000>; /* r1679 */
204 };
205 };
206 /* 4 - 7 unused */
207 };
208};
209
210&i2c1 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213
214 i2c-mux@74 { /* u35 */
215 compatible = "nxp,pca9548";
216 #address-cells = <1>;
217 #size-cells = <0>;
218 reg = <0x74>;
219 i2c-mux-idle-disconnect;
220 /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
221 i2c@0 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg = <0>;
225 };
226 fmcp1_i2c: i2c@1 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 reg = <1>;
230 /* connection to Samtec J51C */
231 /* expected eeprom 0x50 SE cards */
232 };
233 osfp_i2c: i2c@2 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 reg = <2>;
237 /* J362 connector */
238 };
239 i2c@3 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 reg = <3>;
243 /* alternative option DNP - u305 at 0x50 */
244 };
245 i2c@4 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 reg = <4>;
249 /* alternative option DNP - u303 at 0x50 */
250 };
251 i2c@5 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 reg = <5>;
255 /* alternative option DNP - u301 at 0x50 */
256 };
257 qsfpdd_i2c: i2c@6 {
258 #address-cells = <1>;
259 #size-cells = <0>;
260 reg = <6>;
261 /* J1/J2/J355/J354/J359/J358 connectors */
262 };
263 idt8a34001_i2c: i2c@7 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 reg = <7>;
267 /* Via J310 connector */
268 idt_8a34001: phc@5b { /* u219B */
269 compatible = "idt,8a34001";
270 reg = <0x5b>;
271 };
272 };
273 };
274 i2c-mux@75 { /* u322 */
275 compatible = "nxp,pca9548";
276 #address-cells = <1>;
277 #size-cells = <0>;
278 reg = <0x75>;
279 i2c-mux-idle-disconnect;
280 /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
281 sfpdd1_i2c: i2c@0 {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 reg = <0>;
285 /* J350 sfp-dd at 0x50 */
286 };
287 sfpdd2_i2c: i2c@1 {
288 #address-cells = <1>;
289 #size-cells = <0>;
290 reg = <1>;
291 /* J352 sfp-dd at 0x50 */
292 };
293 sfpdd3_i2c: i2c@2 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 reg = <2>;
297 /* J385 sfp-dd at 0x50 */
298 };
299 sfpdd4_i2c: i2c@3 {
300 #address-cells = <1>;
301 #size-cells = <0>;
302 reg = <3>;
303 /* J387 sfp-dd at 0x50 */
304 };
305 rc21008a_gtclk1_i2c: i2c@4 {
306 #address-cells = <1>;
307 #size-cells = <0>;
308 reg = <4>;
309 vc7_1: clock-generator@9 {
310 compatible = "renesas,rc21008a";
311 clock-output-names = "rc21008a-0";
312 reg = <0x9>;
313 #clock-cells = <1>;
314 clocks = <&vc7_xin>;
315 clock-names = "xin";
316 };
317 /* u298 - rc21008a at 0x9 */
318 /* connector J370 */
319 };
320 rc21008a_gtclk2_i2c: i2c@5 {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg = <5>;
324 vc7_2: clock-generator@9 {
325 compatible = "renesas,rc21008a";
326 clock-output-names = "rc21008a-1";
327 reg = <0x9>;
328 #clock-cells = <1>;
329 clocks = <&vc7_xin>;
330 clock-names = "xin";
331 };
332 /* u299 - rc21008a at 0x9 */
333 /* connector J371 */
334 };
335 };
336};