blob: e9419c4fe605c50cd24b7801eb6ce5f4ae9b6161 [file] [log] [blame]
Jan Kiszka4a88eb22021-09-18 08:17:52 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) Siemens AG, 2021
4 *
5 * Authors:
6 * Chao Zeng <chao.zeng@siemens.com>
7 * Jan Kiszka <jan.kiszka@siemens.com>
8 *
9 * Common bits of the IOT2050 Basic and Advanced variants, PG2
10 */
11
12&main_pmx0 {
Jan Kiszkab6fad962024-01-06 13:39:07 +010013 cp2102n_reset_pin_default: cp2102n-reset-default-pins {
Jan Kiszka4a88eb22021-09-18 08:17:52 +020014 pinctrl-single,pins = <
15 /* (AF12) GPIO1_24, used as cp2102 reset */
16 AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
17 >;
18 };
19};
20
21&main_gpio1 {
22 pinctrl-names = "default";
23 pinctrl-0 = <&cp2102n_reset_pin_default>;
24 gpio-line-names =
25 "", "", "", "", "", "", "", "", "", "",
26 "", "", "", "", "", "", "", "", "", "",
27 "", "", "", "", "CP2102N-RESET";
28};
29
30&dss {
31 /* Workaround needed to get DP clock of 154Mhz */
32 assigned-clocks = <&k3_clks 67 0>;
33};
34
35&serdes0 {
36 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
37 assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
38};
39
40&dwc3_0 {
41 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
42 <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
43 phys = <&serdes0 PHY_TYPE_USB3 0>;
44 phy-names = "usb3-phy";
45};
46
Jan Kiszkabeedfdf2021-10-05 12:04:50 +020047&usb0 {
Jan Kiszka4a88eb22021-09-18 08:17:52 +020048 maximum-speed = "super-speed";
49 snps,dis-u1-entry-quirk;
50 snps,dis-u2-entry-quirk;
51};