// SPDX-License-Identifier: GPL-2.0+ | |
/* | |
* dts file for Xilinx ZynqMP zc1751-xm019-dc5 | |
* | |
* (C) Copyright 2015 - 2018, Xilinx, Inc. | |
* | |
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> | |
* Michal Simek <michal.simek@xilinx.com> | |
*/ | |
/dts-v1/; | |
#include "zynqmp.dtsi" | |
#include "zynqmp-clk-ccf.dtsi" | |
/ { | |
model = "ZynqMP zc1751-xm019-dc5 RevA"; | |
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; | |
aliases { | |
ethernet0 = &gem1; | |
gpio0 = &gpio; | |
i2c0 = &i2c0; | |
i2c1 = &i2c1; | |
mmc0 = &sdhci0; | |
serial0 = &uart0; | |
serial1 = &uart1; | |
}; | |
chosen { | |
bootargs = "earlycon"; | |
stdout-path = "serial0:115200n8"; | |
}; | |
memory@0 { | |
device_type = "memory"; | |
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; | |
}; | |
}; | |
&fpd_dma_chan1 { | |
status = "okay"; | |
}; | |
&fpd_dma_chan2 { | |
status = "okay"; | |
}; | |
&fpd_dma_chan3 { | |
status = "okay"; | |
}; | |
&fpd_dma_chan4 { | |
status = "okay"; | |
}; | |
&fpd_dma_chan5 { | |
status = "okay"; | |
}; | |
&fpd_dma_chan6 { | |
status = "okay"; | |
}; | |
&fpd_dma_chan7 { | |
status = "okay"; | |
}; | |
&fpd_dma_chan8 { | |
status = "okay"; | |
}; | |
&gem1 { | |
status = "okay"; | |
phy-handle = <&phy0>; | |
phy-mode = "rgmii-id"; | |
phy0: phy@0 { | |
reg = <0>; | |
}; | |
}; | |
&gpio { | |
status = "okay"; | |
}; | |
&i2c0 { | |
status = "okay"; | |
}; | |
&i2c1 { | |
status = "okay"; | |
}; | |
&sdhci0 { | |
status = "okay"; | |
no-1-8-v; | |
}; | |
&ttc0 { | |
status = "okay"; | |
}; | |
&ttc1 { | |
status = "okay"; | |
}; | |
&ttc2 { | |
status = "okay"; | |
}; | |
&ttc3 { | |
status = "okay"; | |
}; | |
&uart0 { | |
status = "okay"; | |
}; | |
&uart1 { | |
status = "okay"; | |
}; | |
&watchdog0 { | |
status = "okay"; | |
}; |