| // SPDX-License-Identifier: GPL-2.0+ |
| * dts file for Xilinx ZynqMP Mini Configuration |
| * (C) Copyright 2015 - 2020, Xilinx, Inc. |
| * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> |
| * Michal Simek <michal.simek@amd.com> |
| model = "ZynqMP MINI QSPI"; |
| compatible = "xlnx,zynqmp"; |
| stdout-path = "serial0:115200n8"; |
| reg = <0x0 0xfffc0000 0x40000>; |
| compatible = "simple-bus"; |
| compatible = "xlnx,zynqmp-qspi-1.0"; |
| clock-names = "ref_clk", "pclk"; |
| clocks = <&misc_clk &misc_clk>; |
| reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; |
| compatible = "fixed-clock"; |
| clock-frequency = <125000000>; |
| compatible = "n25q512a11", "jedec,spi-nor"; |
| spi-max-frequency = <40000000>; |