| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2018-2019 NXP |
| * Copyright 2022 Linaro |
| */ |
| |
| #include <common.h> |
| #include <command.h> |
| #include <cpu_func.h> |
| #include <errno.h> |
| #include <fsl_esdhc_imx.h> |
| #include <hang.h> |
| #include <image.h> |
| #include <init.h> |
| #include <log.h> |
| #include <mmc.h> |
| #include <spl.h> |
| #include <asm/io.h> |
| #include <asm/arch/clock.h> |
| #include <asm/arch/ddr.h> |
| #include <asm/arch/imx8mp_pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/mach-imx/boot_mode.h> |
| #include <asm/mach-imx/gpio.h> |
| #include <asm/mach-imx/iomux-v3.h> |
| #include <asm/mach-imx/mxc_i2c.h> |
| #include <dm/uclass.h> |
| #include <linux/delay.h> |
| #include <power/pmic.h> |
| #include <power/pca9450.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| int spl_board_boot_device(enum boot_device boot_dev_spl) |
| { |
| #ifdef CONFIG_SPL_BOOTROM_SUPPORT |
| return BOOT_DEVICE_BOOTROM; |
| #else |
| switch (boot_dev_spl) { |
| case SD1_BOOT: |
| case MMC1_BOOT: |
| case SD2_BOOT: |
| case MMC2_BOOT: |
| return BOOT_DEVICE_MMC1; |
| case SD3_BOOT: |
| case MMC3_BOOT: |
| return BOOT_DEVICE_MMC2; |
| case QSPI_BOOT: |
| return BOOT_DEVICE_NOR; |
| case NAND_BOOT: |
| return BOOT_DEVICE_NAND; |
| case USB_BOOT: |
| return BOOT_DEVICE_BOARD; |
| default: |
| return BOOT_DEVICE_NONE; |
| } |
| #endif |
| } |
| |
| void spl_dram_init(void) |
| { |
| ddr_init(&dram_timing); |
| } |
| |
| #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) |
| #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
| struct i2c_pads_info i2c_pad_info1 = { |
| .scl = { |
| .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, |
| .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, |
| .gp = IMX_GPIO_NR(5, 14), |
| }, |
| .sda = { |
| .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, |
| .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, |
| .gp = IMX_GPIO_NR(5, 15), |
| }, |
| }; |
| |
| #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) |
| #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ |
| PAD_CTL_PE | \ |
| PAD_CTL_FSEL2) |
| #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) |
| #define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS | \ |
| PAD_CTL_DSE4) |
| |
| static const iomux_v3_cfg_t usdhc3_pads[] = { |
| MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| }; |
| |
| static const iomux_v3_cfg_t usdhc2_pads[] = { |
| MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), |
| MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), |
| }; |
| |
| #ifndef USDHC3_BASE_ADDR |
| #define USDHC3_BASE_ADDR 0x30B60000 |
| #endif |
| |
| static struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| {USDHC2_BASE_ADDR, 0, 4}, |
| {USDHC3_BASE_ADDR, 0, 8}, |
| }; |
| |
| int board_mmc_init(struct bd_info *bis) |
| { |
| int i, ret; |
| /* |
| * According to the board_mmc_init() the following map is done: |
| * (U-Boot device node) (Physical Port) |
| * mmc0 USDHC1 |
| * mmc1 USDHC2 |
| */ |
| for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| switch (i) { |
| case 0: |
| init_clk_usdhc(1); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| imx_iomux_v3_setup_multiple_pads(usdhc2_pads, |
| ARRAY_SIZE(usdhc2_pads)); |
| gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); |
| gpio_direction_output(USDHC2_PWR_GPIO, 0); |
| udelay(500); |
| gpio_direction_output(USDHC2_PWR_GPIO, 1); |
| gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); |
| gpio_direction_input(USDHC2_CD_GPIO); |
| break; |
| case 1: |
| init_clk_usdhc(2); |
| usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| imx_iomux_v3_setup_multiple_pads(usdhc3_pads, |
| ARRAY_SIZE(usdhc3_pads)); |
| break; |
| default: |
| printf("Warning: you configured more USDHC controllers"); |
| printf("(%d) than supported by the board\n", i + 1); |
| return -EINVAL; |
| } |
| |
| ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| if (ret) |
| return ret; |
| } |
| |
| return 0; |
| } |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| default: |
| break; |
| case USDHC2_BASE_ADDR: |
| ret = !gpio_get_value(USDHC2_CD_GPIO); |
| return ret; |
| } |
| |
| return 1; |
| } |
| |
| int power_init_board(void) |
| { |
| struct udevice *pdev; |
| int ret; |
| |
| ret = pmic_get("pca9450@25", &pdev); |
| if (ret == -ENODEV) { |
| printf("No pmic\n"); |
| return 0; |
| } |
| if (ret != 0) |
| return ret; |
| |
| /* BUCKxOUT_DVS0/1 control BUCK123 output */ |
| pmic_reg_write(pdev, PCA9450_BUCK123_DVS, 0x29); |
| |
| /* |
| * increase VDD_SOC to typical value 0.95V before first |
| * DRAM access, set DVS1 to 0.85v for suspend. |
| * Enable DVS control through PMIC_STBY_REQ and |
| * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) |
| */ |
| pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS0, 0x1C); |
| pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS1, 0x14); |
| pmic_reg_write(pdev, PCA9450_BUCK1CTRL, 0x59); |
| |
| /* Kernel uses OD/OD freq for SOC */ |
| /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ |
| pmic_reg_write(pdev, PCA9450_BUCK2OUT_DVS0, 0x1C); |
| |
| /* set WDOG_B_CFG to cold reset */ |
| pmic_reg_write(pdev, PCA9450_RESET_CTRL, 0xA1); |
| |
| /* Forced enable the I2C level translator*/ |
| pmic_reg_write(pdev, PCA9450_CONFIG2, 0x03); |
| |
| return 0; |
| } |
| |
| void spl_board_init(void) |
| { |
| puts("Normal Boot\n"); |
| } |
| |
| #ifdef CONFIG_SPL_LOAD_FIT |
| int board_fit_config_name_match(const char *name) |
| { |
| /* Just empty function now - can't decide what to choose */ |
| debug("%s: %s\n", __func__, name); |
| |
| return 0; |
| } |
| #endif |
| |
| void board_init_f(ulong dummy) |
| { |
| int ret; |
| |
| arch_cpu_init(); |
| |
| board_early_init_f(); |
| |
| timer_init(); |
| |
| ret = spl_early_init(); |
| if (ret) { |
| debug("spl_init() failed: %d\n", ret); |
| hang(); |
| } |
| |
| preloader_console_init(); |
| |
| enable_tzc380(); |
| |
| power_init_board(); |
| |
| /* DDR initialization */ |
| spl_dram_init(); |
| } |