commit f942636cf84f897e80daad14027efd114823727a
author Bin Meng <bmeng.cn@gmail.com> Wed Jul 10 23:43:13 2019 -0700
committer Andes <uboot@andestech.com> Thu Aug 15 13:42:28 2019 +0800
tree 26cf69a122a61b2a54ff75b6489414353cff1348
parent a27264c281f92c8bc17c6936fbbbbea2bb273d2c

riscv: Access CSRs using CSR numbers

We should prefer accessing CSRs using their CSR numbers
because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR
   numbers as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not
   recognize newly added CSRs by name.

This commit is inspired from Linux kernel commit a3182c91ef4e
("RISC-V: Access CSRs using CSR numbers").

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

arch/riscv/cpu/cpu.c

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e9a8b43..5ca1857 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -7,7 +7,6 @@
 #include <cpu.h>
 #include <dm.h>
 #include <log.h>
-#include <asm/csr.h>
 #include <asm/encoding.h>
 #include <dm/uclass-internal.h>
 
@@ -48,7 +47,7 @@
 	return false;
 #else  /* !CONFIG_CPU */
 #ifdef CONFIG_RISCV_MMODE
-	return csr_read(misa) & (1 << (ext - 'a'));
+	return csr_read(CSR_MISA) & (1 << (ext - 'a'));
 #else  /* !CONFIG_RISCV_MMODE */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
@@ -82,7 +81,7 @@
 	/* Enable FPU */
 	if (supports_extension('d') || supports_extension('f')) {
 		csr_set(MODE_PREFIX(status), MSTATUS_FS);
-		csr_write(fcsr, 0);
+		csr_write(CSR_FCSR, 0);
 	}
 
 	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
@@ -90,11 +89,11 @@
 		 * Enable perf counters for cycle, time,
 		 * and instret counters only
 		 */
-		csr_write(mcounteren, GENMASK(2, 0));
+		csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
 
 		/* Disable paging */
 		if (supports_extension('s'))
-			csr_write(satp, 0);
+			csr_write(CSR_SATP, 0);
 	}
 
 	return 0;

arch/riscv/cpu/start.S

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 60ac8c6..e06db40 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -13,7 +13,6 @@
 #include <config.h>
 #include <common.h>
 #include <elf.h>
-#include <asm/csr.h>
 #include <asm/encoding.h>
 #include <generated/asm-offsets.h>
 
@@ -41,7 +40,7 @@
 .globl _start
 _start:
 #ifdef CONFIG_RISCV_MMODE
-	csrr	a0, mhartid
+	csrr	a0, CSR_MHARTID
 #endif
 
 	/* save hart id and dtb pointer */