[PATCH] Clean up 40EZ/Acadia support
This patch cleans up all the open issue of the preliminary
Acadia support.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index a50d66e..de45ba7 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -2,6 +2,7 @@
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -757,7 +758,6 @@
#endif /* CONFIG_405EP */
#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
-/* test-only... (clean up later when NAND booting is supported) */
#if defined(CONFIG_405EZ)
/********************************************************************
* Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
@@ -786,41 +786,7 @@
mtdcr ocmdsisdpc,r4
isync
-
-#if defined(CONFIG_NAND_SPL)
- /*
- * 405EZ can boot from NAND Flash.
- * If we are booting the SPL (Pre-loader), copy code from
- * the mapped 4K NAND Flash to the OCM
- */
- li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
- mtctr r4
- lis r2,CFG_NAND_BOOT_SPL_SRC@h
- ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
- lis r3,CFG_NAND_BOOT_SPL_DST@h
- ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
-spl_loop:
- lwzu r4,4(r2)
- stwu r4,4(r3)
- bdnz spl_loop
-
- /*
- * Jump to code in OCM Ram
- */
- bl 00f
-00: mflr r10
- lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
- ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
- sub r10,r10,r3
- addi r10,r10,28
- mtlr r10
- blr
-start_ram:
- sync
- isync
-#endif
-#else
-/* ...test-only */
+#else /* CONFIG_405EZ */
/********************************************************************
* Setup OCM - On Chip Memory
*******************************************************************/
@@ -828,14 +794,15 @@
lis r0, 0x7FFF
ori r0, r0, 0xFFFF
mfdcr r3, ocmiscntl /* get instr-side IRAM config */
- mfdcr r4, ocmdscntl /* get data-side IRAM config */
- and r3, r3, r0 /* disable data-side IRAM */
- and r4, r4, r0 /* disable data-side IRAM */
- mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
- mtdcr ocmdscntl, r4 /* set data-side IRAM config */
+ mfdcr r4, ocmdscntl /* get data-side IRAM config */
+ and r3, r3, r0 /* disable data-side IRAM */
+ and r4, r4, r0 /* disable data-side IRAM */
+ mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
+ mtdcr ocmdscntl, r4 /* set data-side IRAM config */
isync
- addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
+ lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
+ ori r3,r3,CFG_OCM_DATA_ADDR@l
mtdcr ocmdsarc, r3
addis r4, 0, 0xC000 /* OCM data area enabled */
mtdcr ocmdscntl, r4