board/tcl/sl50/board.c - filogic/uboot - Gitiles

 // SPDX-License-Identifier: GPL-2.0+
 /*
  * board.c
  *
  * Board functions for TCL SL50 board
  *
  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  */

 #include <common.h>
 #include <env.h>
 #include <errno.h>
 #include <init.h>
 #include <net.h>
 #include <serial.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
 #include <power/tps65217.h>
 #include <power/tps65910.h>
 #include <env_internal.h>
 #include <watchdog.h>
 #include "board.h"

 DECLARE_GLOBAL_DATA_PTR;

 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

 #ifndef CONFIG_SKIP_LOWLEVEL_INIT

 static const struct ddr_data ddr3_sl50_data = {
 	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 };

 static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
 	.cmd0csratio = MT41K256M16HA125E_RATIO,
 	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

 	.cmd1csratio = MT41K256M16HA125E_RATIO,
 	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

 	.cmd2csratio = MT41K256M16HA125E_RATIO,
 	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 };

 static struct emif_regs ddr3_sl50_emif_reg_data = {
 	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 };

 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
 	/* break into full u-boot on 'c' */
 	if (serial_tstc() && serial_getc() == 'c')
 		return 1;

 #ifdef CONFIG_SPL_ENV_SUPPORT
 	env_init();
 	env_load();
 	if (env_get_yesno("boot_os") != 1)
 		return 1;
 #endif

 	return 0;
 }
 #endif

 #define OSC	(V_OSCK/1000000)
 const struct dpll_params dpll_ddr_sl50 = {
 		400, OSC-1, 1, -1, -1, -1, -1};

 void am33xx_spl_board_init(void)
 {
 	int mpu_vdd;

 	/* Get the frequency */
 	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);

 	/* BeagleBone PMIC Code */
 	int usb_cur_lim;

 	if (i2c_probe(TPS65217_CHIP_PM))
 		return;

 	/*
 	 * Increase USB current limit to 1300mA or 1800mA and set
 	 * the MPU voltage controller as needed.
 	 */
 	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 	} else {
 		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 	}

 	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 			       TPS65217_POWER_PATH,
 			       usb_cur_lim,
 			       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 		puts("tps65217_reg_write failure\n");

 	/* Set DCDC3 (CORE) voltage to 1.125V */
 	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 				    TPS65217_DCDC_VOLT_SEL_1125MV)) {
 		puts("tps65217_voltage_update failure\n");
 		return;
 	}

 	/* Set CORE Frequencies to OPP100 */
 	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);

 	/* Set DCDC2 (MPU) voltage */
 	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 		puts("tps65217_voltage_update failure\n");
 		return;
 	}

 	/*
 	 * Set LDO3 to 1.8V and LDO4 to 3.3V
 	 */
 	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 			       TPS65217_DEFLS1,
 			       TPS65217_LDO_VOLTAGE_OUT_1_8,
 			       TPS65217_LDO_MASK))
 		puts("tps65217_reg_write failure\n");

 	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 			       TPS65217_DEFLS2,
 			       TPS65217_LDO_VOLTAGE_OUT_3_3,
 			       TPS65217_LDO_MASK))
 		puts("tps65217_reg_write failure\n");

 	/* Set MPU Frequency to what we detected now that voltages are set */
 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }

 const struct dpll_params *get_dpll_ddr_params(void)
 {
 	enable_i2c0_pin_mux();
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

 	return &dpll_ddr_sl50;
 }

 void set_uart_mux_conf(void)
 {
 #if CONFIG_CONS_INDEX == 1
 	enable_uart0_pin_mux();
 #elif CONFIG_CONS_INDEX == 2
 	enable_uart1_pin_mux();
 #elif CONFIG_CONS_INDEX == 3
 	enable_uart2_pin_mux();
 #elif CONFIG_CONS_INDEX == 4
 	enable_uart3_pin_mux();
 #elif CONFIG_CONS_INDEX == 5
 	enable_uart4_pin_mux();
 #elif CONFIG_CONS_INDEX == 6
 	enable_uart5_pin_mux();
 #endif
 }

 void set_mux_conf_regs(void)
 {
 	enable_board_pin_mux();
 }

 const struct ctrl_ioregs ioregs_evmsk = {
 	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 };

 const struct ctrl_ioregs ioregs_bonelt = {
 	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 };

 const struct ctrl_ioregs ioregs_evm15 = {
 	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 };

 const struct ctrl_ioregs ioregs = {
 	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 };

 void sdram_init(void)
 {
 	config_ddr(400, &ioregs_bonelt,
 		   &ddr3_sl50_data,
 		   &ddr3_sl50_cmd_ctrl_data,
 		   &ddr3_sl50_emif_reg_data, 0);
 }
 #endif

 /*
  * Basic board specific setup.  Pinmux has been handled already.
  */
 int board_init(void)
 {
 #if defined(CONFIG_HW_WATCHDOG)
 	hw_watchdog_init();
 #endif

 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 	return 0;
 }

 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
 	return 0;
 }
 #endif

 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
 static void cpsw_control(int enabled)
 {
 	/* VTP can be added here */

 	return;
 }

 static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
 		.phy_addr	= 0,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
 		.phy_addr	= 1,
 	},
 };

 static struct cpsw_platform_data cpsw_data = {
 	.mdio_base		= CPSW_MDIO_BASE,
 	.cpsw_base		= CPSW_BASE,
 	.mdio_div		= 0xff,
 	.channels		= 8,
 	.cpdma_reg_ofs		= 0x800,
 	.slaves			= 1,
 	.slave_data		= cpsw_slaves,
 	.ale_reg_ofs		= 0xd00,
 	.ale_entries		= 1024,
 	.host_port_reg_ofs	= 0x108,
 	.hw_stats_reg_ofs	= 0x900,
 	.bd_ram_ofs		= 0x2000,
 	.mac_control		= (1 << 5),
 	.control		= cpsw_control,
 	.host_port_num		= 0,
 	.version		= CPSW_CTRL_VERSION_2,
 };
 #endif

 /*
  * This function will:
  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
  * in the environment
  * Perform fixups to the PHY present on certain boards.  We only need this
  * function in:
  * - SPL with either CPSW or USB ethernet support
  * - Full U-Boot, with either CPSW or USB ethernet
  * Build in only these cases to avoid warnings about unused variables
  * when we build an SPL that has neither option but full U-Boot will.
  */
 #if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \
 		&& defined(CONFIG_SPL_BUILD)) || \
 	((defined(CONFIG_DRIVER_TI_CPSW) || \
 	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 	 !defined(CONFIG_SPL_BUILD))
 int board_eth_init(struct bd_info *bis)
 {
 	int rv, n = 0;
 	uint8_t mac_addr[6];
 	uint32_t mac_hi, mac_lo;

 	/* try reading mac address from efuse */
 	mac_lo = readl(&cdev->macid0l);
 	mac_hi = readl(&cdev->macid0h);
 	mac_addr[0] = mac_hi & 0xFF;
 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
 	if (!env_get("ethaddr")) {
 		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

 		if (is_valid_ethaddr(mac_addr))
 			eth_env_set_enetaddr("ethaddr", mac_addr);
 	}

 #ifdef CONFIG_DRIVER_TI_CPSW

 	mac_lo = readl(&cdev->macid1l);
 	mac_hi = readl(&cdev->macid1h);
 	mac_addr[0] = mac_hi & 0xFF;
 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

 	if (!env_get("eth1addr")) {
 		if (is_valid_ethaddr(mac_addr))
 			eth_env_set_enetaddr("eth1addr", mac_addr);
 	}


 	writel(MII_MODE_ENABLE, &cdev->miisel);
 	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 				PHY_INTERFACE_MODE_MII;

 	rv = cpsw_register(&cpsw_data);
 	if (rv < 0)
 		printf("Error %d registering CPSW switch\n", rv);
 	else
 		n += rv;
 #endif

 	/*
 	 *
 	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
 	 * operating points.  So we must set the TX clock delay feature
 	 * in the AR8051 PHY.  Since we only support a single ethernet
 	 * device in U-Boot, we only do this for the first instance.
 	 */
 #define AR8051_PHY_DEBUG_ADDR_REG	0x1d
 #define AR8051_PHY_DEBUG_DATA_REG	0x1e
 #define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
 #define AR8051_RGMII_TX_CLK_DLY		0x100

 #endif
 #if defined(CONFIG_USB_ETHER) && \
 	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
 	if (is_valid_ether_addr(mac_addr))
 		eth_env_set_enetaddr("usbnet_devaddr", mac_addr);

 	rv = usb_eth_initialize(bis);
 	if (rv < 0)
 		printf("Error %d registering USB_ETHER\n", rv);
 	else
 		n += rv;
 #endif
 	return n;
 }
 #endif
	// SPDX-License-Identifier: GPL-2.0+
	/*
	* board.c
	*
	* Board functions for TCL SL50 board
	*
	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	*/

	#include <common.h>
	#include <env.h>
	#include <errno.h>
	#include <init.h>
	#include <net.h>
	#include <serial.h>
	#include <spl.h>
	#include <asm/arch/cpu.h>
	#include <asm/arch/hardware.h>
	#include <asm/arch/omap.h>
	#include <asm/arch/ddr_defs.h>
	#include <asm/arch/clock.h>
	#include <asm/arch/gpio.h>
	#include <asm/arch/mmc_host_def.h>
	#include <asm/arch/sys_proto.h>
	#include <asm/arch/mem.h>
	#include <asm/global_data.h>
	#include <asm/io.h>
	#include <asm/emif.h>
	#include <asm/gpio.h>
	#include <i2c.h>
	#include <miiphy.h>
	#include <cpsw.h>
	#include <power/tps65217.h>
	#include <power/tps65910.h>
	#include <env_internal.h>
	#include <watchdog.h>
	#include "board.h"

	DECLARE_GLOBAL_DATA_PTR;

	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;

	#ifndef CONFIG_SKIP_LOWLEVEL_INIT

	static const struct ddr_data ddr3_sl50_data = {
	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
	};

	static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
	.cmd0csratio = MT41K256M16HA125E_RATIO,
	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd1csratio = MT41K256M16HA125E_RATIO,
	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd2csratio = MT41K256M16HA125E_RATIO,
	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	};

	static struct emif_regs ddr3_sl50_emif_reg_data = {
	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
	};

	#ifdef CONFIG_SPL_OS_BOOT
	int spl_start_uboot(void)
	{
	/* break into full u-boot on 'c' */
	if (serial_tstc() && serial_getc() == 'c')
	return 1;

	#ifdef CONFIG_SPL_ENV_SUPPORT
	env_init();
	env_load();
	if (env_get_yesno("boot_os") != 1)
	return 1;
	#endif

	return 0;
	}
	#endif

	#define OSC (V_OSCK/1000000)
	const struct dpll_params dpll_ddr_sl50 = {
	400, OSC-1, 1, -1, -1, -1, -1};

	void am33xx_spl_board_init(void)
	{
	int mpu_vdd;

	/* Get the frequency */
	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);

	/* BeagleBone PMIC Code */
	int usb_cur_lim;

	if (i2c_probe(TPS65217_CHIP_PM))
	return;

	/*
	* Increase USB current limit to 1300mA or 1800mA and set
	* the MPU voltage controller as needed.
	*/
	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
	usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
	mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
	} else {
	usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
	mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
	}

	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
	TPS65217_POWER_PATH,
	usb_cur_lim,
	TPS65217_USB_INPUT_CUR_LIMIT_MASK))
	puts("tps65217_reg_write failure\n");

	/* Set DCDC3 (CORE) voltage to 1.125V */
	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
	TPS65217_DCDC_VOLT_SEL_1125MV)) {
	puts("tps65217_voltage_update failure\n");
	return;
	}

	/* Set CORE Frequencies to OPP100 */
	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);

	/* Set DCDC2 (MPU) voltage */
	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
	puts("tps65217_voltage_update failure\n");
	return;
	}

	/*
	* Set LDO3 to 1.8V and LDO4 to 3.3V
	*/
	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
	TPS65217_DEFLS1,
	TPS65217_LDO_VOLTAGE_OUT_1_8,
	TPS65217_LDO_MASK))
	puts("tps65217_reg_write failure\n");

	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
	TPS65217_DEFLS2,
	TPS65217_LDO_VOLTAGE_OUT_3_3,
	TPS65217_LDO_MASK))
	puts("tps65217_reg_write failure\n");

	/* Set MPU Frequency to what we detected now that voltages are set */
	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
	}

	const struct dpll_params *get_dpll_ddr_params(void)
	{
	enable_i2c0_pin_mux();
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	return &dpll_ddr_sl50;
	}

	void set_uart_mux_conf(void)
	{
	#if CONFIG_CONS_INDEX == 1
	enable_uart0_pin_mux();
	#elif CONFIG_CONS_INDEX == 2
	enable_uart1_pin_mux();
	#elif CONFIG_CONS_INDEX == 3
	enable_uart2_pin_mux();
	#elif CONFIG_CONS_INDEX == 4
	enable_uart3_pin_mux();
	#elif CONFIG_CONS_INDEX == 5
	enable_uart4_pin_mux();
	#elif CONFIG_CONS_INDEX == 6
	enable_uart5_pin_mux();
	#endif
	}

	void set_mux_conf_regs(void)
	{
	enable_board_pin_mux();
	}

	const struct ctrl_ioregs ioregs_evmsk = {
	.cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
	.cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
	.cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
	.dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
	.dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
	};

	const struct ctrl_ioregs ioregs_bonelt = {
	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	};

	const struct ctrl_ioregs ioregs_evm15 = {
	.cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	.cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	.cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	.dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	.dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
	};

	const struct ctrl_ioregs ioregs = {
	.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
	};

	void sdram_init(void)
	{
	config_ddr(400, &ioregs_bonelt,
	&ddr3_sl50_data,
	&ddr3_sl50_cmd_ctrl_data,
	&ddr3_sl50_emif_reg_data, 0);
	}
	#endif

	/*
	* Basic board specific setup. Pinmux has been handled already.
	*/
	int board_init(void)
	{
	#if defined(CONFIG_HW_WATCHDOG)
	hw_watchdog_init();
	#endif

	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	return 0;
	}

	#ifdef CONFIG_BOARD_LATE_INIT
	int board_late_init(void)
	{
	return 0;
	}
	#endif

	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	(defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
	static void cpsw_control(int enabled)
	{
	/* VTP can be added here */

	return;
	}

	static struct cpsw_slave_data cpsw_slaves[] = {
	{
	.slave_reg_ofs = 0x208,
	.sliver_reg_ofs = 0xd80,
	.phy_addr = 0,
	},
	{
	.slave_reg_ofs = 0x308,
	.sliver_reg_ofs = 0xdc0,
	.phy_addr = 1,
	},
	};

	static struct cpsw_platform_data cpsw_data = {
	.mdio_base = CPSW_MDIO_BASE,
	.cpsw_base = CPSW_BASE,
	.mdio_div = 0xff,
	.channels = 8,
	.cpdma_reg_ofs = 0x800,
	.slaves = 1,
	.slave_data = cpsw_slaves,
	.ale_reg_ofs = 0xd00,
	.ale_entries = 1024,
	.host_port_reg_ofs = 0x108,
	.hw_stats_reg_ofs = 0x900,
	.bd_ram_ofs = 0x2000,
	.mac_control = (1 << 5),
	.control = cpsw_control,
	.host_port_num = 0,
	.version = CPSW_CTRL_VERSION_2,
	};
	#endif

	/*
	* This function will:
	* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
	* in the environment
	* Perform fixups to the PHY present on certain boards. We only need this
	* function in:
	* - SPL with either CPSW or USB ethernet support
	* - Full U-Boot, with either CPSW or USB ethernet
	* Build in only these cases to avoid warnings about unused variables
	* when we build an SPL that has neither option but full U-Boot will.
	*/
	#if ((defined(CONFIG_SPL_ETH) \|\| defined(CONFIG_SPL_USB_ETHER)) \
	&& defined(CONFIG_SPL_BUILD)) \|\| \
	((defined(CONFIG_DRIVER_TI_CPSW) \|\| \
	defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
	!defined(CONFIG_SPL_BUILD))
	int board_eth_init(struct bd_info *bis)
	{
	int rv, n = 0;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;

	/* try reading mac address from efuse */
	mac_lo = readl(&cdev->macid0l);
	mac_hi = readl(&cdev->macid0h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	(defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
	if (!env_get("ethaddr")) {
	printf("<ethaddr> not set. Validating first E-fuse MAC\n");

	if (is_valid_ethaddr(mac_addr))
	eth_env_set_enetaddr("ethaddr", mac_addr);
	}

	#ifdef CONFIG_DRIVER_TI_CPSW

	mac_lo = readl(&cdev->macid1l);
	mac_hi = readl(&cdev->macid1h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

	if (!env_get("eth1addr")) {
	if (is_valid_ethaddr(mac_addr))
	eth_env_set_enetaddr("eth1addr", mac_addr);
	}


	writel(MII_MODE_ENABLE, &cdev->miisel);
	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
	PHY_INTERFACE_MODE_MII;

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
	printf("Error %d registering CPSW switch\n", rv);
	else
	n += rv;
	#endif

	/*
	*
	* CPSW RGMII Internal Delay Mode is not supported in all PVT
	* operating points. So we must set the TX clock delay feature
	* in the AR8051 PHY. Since we only support a single ethernet
	* device in U-Boot, we only do this for the first instance.
	*/
	#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
	#define AR8051_PHY_DEBUG_DATA_REG 0x1e
	#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
	#define AR8051_RGMII_TX_CLK_DLY 0x100

	#endif
	#if defined(CONFIG_USB_ETHER) && \
	(!defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_SPL_USB_ETHER))
	if (is_valid_ether_addr(mac_addr))
	eth_env_set_enetaddr("usbnet_devaddr", mac_addr);

	rv = usb_eth_initialize(bis);
	if (rv < 0)
	printf("Error %d registering USB_ETHER\n", rv);
	else
	n += rv;
	#endif
	return n;
	}
	#endif