| config ARCH_LS1012A |
| bool |
| select FSL_LSCH2 |
| select SYS_FSL_MMDC |
| select SYS_FSL_ERRATUM_A010315 |
| |
| config ARCH_LS1043A |
| bool |
| select FSL_LSCH2 |
| select SYS_FSL_ERRATUM_A010315 |
| select SYS_FSL_ERRATUM_A010539 |
| |
| config ARCH_LS1046A |
| bool |
| select FSL_LSCH2 |
| select SYS_FSL_ERRATUM_A010539 |
| |
| config ARCH_LS2080A |
| bool |
| select FSL_LSCH3 |
| |
| config FSL_LSCH2 |
| bool |
| |
| config FSL_LSCH3 |
| bool |
| |
| menu "Layerscape architecture" |
| depends on FSL_LSCH2 || FSL_LSCH3 |
| |
| config SYS_FSL_MMDC |
| bool |
| |
| config SYS_FSL_ERRATUM_A010315 |
| bool "Workaround for PCIe erratum A010315" |
| |
| config SYS_FSL_ERRATUM_A010539 |
| bool "Workaround for PIN MUX erratum A010539" |
| |
| config MAX_CPUS |
| int "Maximum number of CPUs permitted for Layerscape" |
| default 4 if ARCH_LS1043A |
| default 4 if ARCH_LS1046A |
| default 16 if ARCH_LS2080A |
| default 1 |
| help |
| Set this number to the maximum number of possible CPUs in the SoC. |
| SoCs may have multiple clusters with each cluster may have multiple |
| ports. If some ports are reserved but higher ports are used for |
| cores, count the reserved ports. This will allocate enough memory |
| in spin table to properly handle all cores. |
| |
| endmenu |