| commit | eeef27450032072c4d040ea9f870bd675cefa186 | [log] [tgz] |
|---|---|---|
| author | Giulio Benetti <giulio.benetti@benettiengineering.com> | Wed Apr 08 17:10:07 2020 +0200 |
| committer | Stefano Babic <sbabic@denx.de> | Sat Apr 18 12:54:43 2020 +0200 |
| tree | a98df4f6e9bc3d893e7a9625e38f7377d40370b0 | |
| parent | e5ad5e809e10865819e63434234b94decc66c73a [diff] |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>