tree a98df4f6e9bc3d893e7a9625e38f7377d40370b0
parent e5ad5e809e10865819e63434234b94decc66c73a
author Giulio Benetti <giulio.benetti@benettiengineering.com> 1586358607 +0200
committer Stefano Babic <sbabic@denx.de> 1587207283 +0200

clk: imx: pllv3: add enable_bit

pllv3 PLLs have powerdown/up bits but enable bits too. Specifically
"enable bit" enable the pll output, so when dis/enabling pll by
setting/clearing power_bit we must also set/clear enable_bit.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>