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git01.mediatek.com / filogic / uboot / edfb5dee8cf98b00d808fe2215225acaf02803b3 / . / board / freescale / t104xrdb / t1042_pi_sd_rcw.cfg
blob: bbce9a36930b5016a4278f70c8ca471fb3d81962 [file] [log] [blame]
#PBL preamble and RCW header
aa55aa55 010e0100
# serdes protocol 0x06
0c18000e 0e000000 00000000 00000000
06000002 00400002 68106000 01000000
00000000 00000000 00000000 00030810
00000000 01fe0a06 00000000 00000000