| /* SPDX-License-Identifier: GPL-2.0+ */ |
| * eInfochips Ltd. <www.einfochips.com> |
| * Written-by: Ajay Bhargav <contact@8051projects.net> |
| * Marvell Semiconductor <www.marvell.com> |
| * GPIO Register map for Marvell SOCs |
| u32 gplr; /* Pin Level Register - 0x0000 */ |
| u32 gpdr; /* Pin Direction Register - 0x000C */ |
| u32 gpsr; /* Pin Output Set Register - 0x0018 */ |
| u32 gpcr; /* Pin Output Clear Register - 0x0024 */ |
| u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ |
| u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ |
| u32 gedr; /* Edge Detect Status Register - 0x0048 */ |
| u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ |
| u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ |
| u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable |
| u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable |
| u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable |
| u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable |
| u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ |
| #endif /* __MVGPIO_H__ */ |