| commit | eaedac086c71d5e0acdf5e938bf6254d5ec3ba20 | [log] [tgz] |
|---|---|---|
| author | Franck Jullien <franck.jullien@gmail.com> | Wed May 21 22:43:49 2014 +0200 |
| committer | Tom Rini <trini@ti.com> | Thu Jun 05 14:44:56 2014 -0400 |
| tree | e780e1d48bde6ffeef1aae67acffb2e76a0c66d3 | |
| parent | cdfc5768119648c68942c0e1bb52beb3677d7b6e [diff] |
openrisc: update SPR registers definition The OpenRISC architecture specification v1.0 defines new SPR registers. This patch adds registers definition for group 0 and update bit definitions for the CPU configuration register. Signed-off-by: Franck Jullien <franck.jullien@gmail.com>