tree e780e1d48bde6ffeef1aae67acffb2e76a0c66d3
parent cdfc5768119648c68942c0e1bb52beb3677d7b6e
author Franck Jullien <franck.jullien@gmail.com> 1400705029 +0200
committer Tom Rini <trini@ti.com> 1401993896 -0400

openrisc: update SPR registers definition

The OpenRISC architecture specification v1.0 defines
new SPR registers. This patch adds registers definition
for group 0 and update bit definitions for the CPU
configuration register.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>