| // SPDX-License-Identifier: GPL-2.0+ |
| * Copyright (C) 2013-2014 Panasonic Corporation |
| * Copyright (C) 2015-2016 Socionext Inc. |
| int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) |
| * Set DPLL SSC parameters for DPLLCTRL3 |
| tmp = readl(sc_base + SC_DPLLCTRL3); |
| writel(tmp, sc_base + SC_DPLLCTRL3); |
| * Set DPLL SSC parameters for DPLLCTRL |
| * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) |
| * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) |
| tmp = readl(sc_base + SC_DPLLCTRL); |
| #ifdef DPLL_SSC_RATE_1PER |
| writel(tmp, sc_base + SC_DPLLCTRL); |
| * Set DPLL SSC parameters for DPLLCTRL2 |
| * [26:20] SSC_M 79 (0x4f) |
| * [19:0] SSC_K 964689 (0xeb851) |
| tmp = readl(sc_base + SC_DPLLCTRL2); |
| writel(tmp, sc_base + SC_DPLLCTRL2); |
| /* Wait 500 usec until dpll gets stable */ |