| /* |
| * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| |
| * You should have received a copy of the GNU General Public License along |
| * with this program; if not, write to the Free Software Foundation, Inc., |
| * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
| */ |
| |
| #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ |
| #define __ASM_ARCH_MX6_IMX_REGS_H__ |
| |
| #define ROMCP_ARB_BASE_ADDR 0x00000000 |
| #define ROMCP_ARB_END_ADDR 0x000FFFFF |
| #define CAAM_ARB_BASE_ADDR 0x00100000 |
| #define CAAM_ARB_END_ADDR 0x00103FFF |
| #define APBH_DMA_ARB_BASE_ADDR 0x00110000 |
| #define APBH_DMA_ARB_END_ADDR 0x00117FFF |
| #define HDMI_ARB_BASE_ADDR 0x00120000 |
| #define HDMI_ARB_END_ADDR 0x00128FFF |
| #define GPU_3D_ARB_BASE_ADDR 0x00130000 |
| #define GPU_3D_ARB_END_ADDR 0x00133FFF |
| #define GPU_2D_ARB_BASE_ADDR 0x00134000 |
| #define GPU_2D_ARB_END_ADDR 0x00137FFF |
| #define DTCP_ARB_BASE_ADDR 0x00138000 |
| #define DTCP_ARB_END_ADDR 0x0013BFFF |
| |
| /* GPV - PL301 configuration ports */ |
| #define GPV2_BASE_ADDR 0x00200000 |
| #define GPV3_BASE_ADDR 0x00300000 |
| #define GPV4_BASE_ADDR 0x00800000 |
| #define IRAM_BASE_ADDR 0x00900000 |
| #define SCU_BASE_ADDR 0x00A00000 |
| #define IC_INTERFACES_BASE_ADDR 0x00A00100 |
| #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 |
| #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 |
| #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 |
| #define GPV0_BASE_ADDR 0x00B00000 |
| #define GPV1_BASE_ADDR 0x00C00000 |
| #define PCIE_ARB_BASE_ADDR 0x01000000 |
| #define PCIE_ARB_END_ADDR 0x01FFFFFF |
| |
| #define AIPS1_ARB_BASE_ADDR 0x02000000 |
| #define AIPS1_ARB_END_ADDR 0x020FFFFF |
| #define AIPS2_ARB_BASE_ADDR 0x02100000 |
| #define AIPS2_ARB_END_ADDR 0x021FFFFF |
| #define SATA_ARB_BASE_ADDR 0x02200000 |
| #define SATA_ARB_END_ADDR 0x02203FFF |
| #define OPENVG_ARB_BASE_ADDR 0x02204000 |
| #define OPENVG_ARB_END_ADDR 0x02207FFF |
| #define HSI_ARB_BASE_ADDR 0x02208000 |
| #define HSI_ARB_END_ADDR 0x0220BFFF |
| #define IPU1_ARB_BASE_ADDR 0x02400000 |
| #define IPU1_ARB_END_ADDR 0x027FFFFF |
| #define IPU2_ARB_BASE_ADDR 0x02800000 |
| #define IPU2_ARB_END_ADDR 0x02BFFFFF |
| #define WEIM_ARB_BASE_ADDR 0x08000000 |
| #define WEIM_ARB_END_ADDR 0x0FFFFFFF |
| |
| #define MMDC0_ARB_BASE_ADDR 0x10000000 |
| #define MMDC0_ARB_END_ADDR 0x7FFFFFFF |
| #define MMDC1_ARB_BASE_ADDR 0x80000000 |
| #define MMDC1_ARB_END_ADDR 0xFFFFFFFF |
| |
| /* Defines for Blocks connected via AIPS (SkyBlue) */ |
| #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR |
| #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR |
| #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR |
| #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR |
| |
| #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) |
| #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) |
| #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) |
| #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) |
| #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) |
| #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) |
| #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) |
| #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) |
| #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) |
| #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) |
| #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) |
| #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) |
| #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) |
| #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) |
| #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) |
| |
| #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) |
| #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) |
| #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) |
| #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) |
| #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) |
| #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) |
| #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) |
| #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) |
| #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) |
| #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) |
| #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) |
| #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) |
| #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) |
| #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) |
| #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) |
| #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) |
| #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) |
| #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) |
| #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) |
| #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) |
| #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) |
| #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) |
| #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) |
| #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) |
| #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) |
| #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) |
| #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) |
| #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) |
| #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) |
| |
| #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) |
| #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) |
| #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) |
| #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) |
| #define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) |
| #define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) |
| #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) |
| #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) |
| #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) |
| #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) |
| #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) |
| #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) |
| #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) |
| #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) |
| #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) |
| #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) |
| #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) |
| #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) |
| #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) |
| #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) |
| #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) |
| #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) |
| #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) |
| #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) |
| #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) |
| #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) |
| #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) |
| #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) |
| #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) |
| #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) |
| #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) |
| #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) |
| #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) |
| #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) |
| #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) |
| #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) |
| |
| #define CHIP_REV_1_0 0x10 |
| #define IRAM_SIZE 0x00040000 |
| #define IMX_IIM_BASE OCOTP_BASE_ADDR |
| |
| #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
| #include <asm/types.h> |
| |
| extern void imx_get_mac_from_fuse(unsigned char *mac); |
| |
| /* System Reset Controller (SRC) */ |
| struct src { |
| u32 scr; |
| u32 sbmr1; |
| u32 srsr; |
| u32 reserved1[2]; |
| u32 sisr; |
| u32 simr; |
| u32 sbmr2; |
| u32 gpr1; |
| u32 gpr2; |
| u32 gpr3; |
| u32 gpr4; |
| u32 gpr5; |
| u32 gpr6; |
| u32 gpr7; |
| u32 gpr8; |
| u32 gpr9; |
| u32 gpr10; |
| }; |
| |
| struct iim_regs { |
| u32 ctrl; |
| u32 ctrl_set; |
| u32 ctrl_clr; |
| u32 ctrl_tog; |
| u32 timing; |
| u32 rsvd0[3]; |
| u32 data; |
| u32 rsvd1[3]; |
| u32 read_ctrl; |
| u32 rsvd2[3]; |
| u32 fuse_data; |
| u32 rsvd3[3]; |
| u32 sticky; |
| u32 rsvd4[3]; |
| u32 scs; |
| u32 scs_set; |
| u32 scs_clr; |
| u32 scs_tog; |
| u32 crc_addr; |
| u32 rsvd5[3]; |
| u32 crc_value; |
| u32 rsvd6[3]; |
| u32 version; |
| u32 rsvd7[0xd8]; |
| |
| struct fuse_bank { |
| u32 fuse_regs[0x20]; |
| } bank[15]; |
| }; |
| |
| struct fuse_bank4_regs { |
| u32 sjc_resp_low; |
| u32 rsvd0[3]; |
| u32 sjc_resp_high; |
| u32 rsvd1[3]; |
| u32 mac_addr_low; |
| u32 rsvd2[3]; |
| u32 mac_addr_high; |
| u32 rsvd3[0x13]; |
| }; |
| |
| #endif /* __ASSEMBLER__*/ |
| #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ |