arch/arm/dts/zynqmp-dlc21-revA.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx ZynqMP DLC21 revA
 *
 * (C) Copyright 2019 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */
/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/ {
	model = "Smartlynq+ DLC21 RevA";
	compatible = "xlnx,zynqmp-dlc21-revA", "xlnx,zynqmp-dlc21",
		     "xlnx,zynqmp";

	aliases {
		ethernet0 = &gem0;
		gpio0 = &gpio;
		i2c0 = &i2c0;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
		rtc0 = &rtc;
		serial0 = &uart0;
		serial2 = &dcc;
		usb0 = &usb0;
		usb1 = &usb1;
		spi0 = &spi0;
		nvmem0 = &eeprom;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0 0 0 0x80000000>, <0x8 0 0x3 0x80000000>;
	};

	si5332_1: si5332_1 { /* clk0_sgmii - u142 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
	};

	si5332_2: si5332_2 { /* clk1_usb - u142 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};
};

&sdhci0 { /* emmc MIO 13-23 - with some settings  16GB */
	status = "okay";
	non-removable;
	disable-wp;
	bus-width = <8>;
	xlnx,mio-bank = <0>;
};

&sdhci1 { /* sd1 MIO45-51 cd in place */
	status = "okay";
	no-1-8-v;
	disable-wp;
	xlnx,mio-bank = <1>;
};

&psgtr {
	status = "okay";
	/* sgmii, usb3 */
	clocks = <&si5332_1>, <&si5332_2>;
	clock-names = "ref0", "ref1";
};

&uart0 { /* uart0 MIO38-39 */
	status = "okay";
	bootph-all;
};

&gem0 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "sgmii"; /* DTG generates this properly  1512 */
	is-internal-pcspma;
	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		/* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
		phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&gpio {
	status = "okay";
	gpio-line-names = "", "", "", "", "", /* 0 - 4 */
		  "", "", "", "", "", /* 5 - 9 */
		  "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
		  "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
		  "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
		  "", "DISP_SCL", "DISP_DC_B", "DISP_RES_B", "DISP_CS_B", /* 25 - 29 */
		  "", "DISP_SDI", "SYSTEM_RST_R_B", "", "I2C0_SCL", /* 30 - 34 */
		  "I2C0_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
		  "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
		  "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
		  "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
		  "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
		  "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
		  "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
		  "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
		  "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
		  "", "", /* 78 - 79 */
		  "", "", "", "", "", /* 80 - 84 */
		  "", "", "", "", "", /* 85 -89 */
		  "", "", "", "", "", /* 90 - 94 */
		  "", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
		  "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
		  "", "", "", "", "", /* 105 - 109 */
		  "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
		  "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
		  "", "", "", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
		  "SYSCTLR_UTIL_2V5_EN", "", "", "", "", /* 125 - 129 */
		  "", "", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "", /* 130 - 134 */
		  "", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
		  "", "", "SYSCTLR_ETH_RESET_B", "", "", /* 140 - 144 */
		  "", "", "", "", "", /* 145 - 149 */
		  "", "", "", "", "", /* 150 - 154 */
		  "", "", "", "", "", /* 155 - 159 */
		  "", "", "", "", "", /* 160 - 164 */
		  "", "", "", "", "", /* 165 - 169 */
		  "", "", "", ""; /* 170 - 173 */
};

&i2c0 { /* MIO34/35 */
	status = "okay";
	clock-frequency = <400000>;

	jtag_vref: mcp4725@62 {
		compatible = "microchip,mcp4725";
		reg = <0x62>;
		vref-millivolt = <3300>;
	};

	eeprom: eeprom@50 { /* u46 */
		compatible = "atmel,24c32";
		reg = <0x50>;
	};
	/* u138 - TUSB320IRWBR - for USB-C */
};

&usb0 {
	status = "okay";
};

&dwc3_0 {
	status = "okay";
	dr_mode = "peripheral";
	snps,dis_u2_susphy_quirk;
	snps,dis_u3_susphy_quirk;
	maximum-speed = "super-speed";
	phy-names = "usb3-phy";
	phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
};

&usb1 {
	status = "disabled"; /* Any unknown issue with USB-C */
};

&dwc3_1 {
	/delete-property/ phy-names ;
	/delete-property/ phys ;
	dr_mode = "host";
	maximum-speed = "high-speed";
	snps,dis_u2_susphy_quirk ;
	snps,dis_u3_susphy_quirk ;
	status = "okay";
};

&xilinx_ams {
	status = "okay";
};

&ams_ps {
	status = "okay";
};

&ams_pl {
	status = "okay";
};

&spi0 {
	status = "okay";
	is-decoded-cs = <0>;
	num-cs = <1>;
	bootph-all;
	displayspi@0 {
		compatible = "syncoam,seps525";
		bootph-all;
		reg = <0>;
		status = "okay";
		spi-max-frequency = <10000000>;
		spi-cpol;
		spi-cpha;
		rotate = <0>;
		fps = <50>;
		buswidth = <8>;
		txbuflen = <64000>;
		reset-gpios = <&gpio 0x1c GPIO_ACTIVE_LOW>;
		dc-gpios = <&gpio 0x1b GPIO_ACTIVE_HIGH>;
		debug = <0>;
	};
};