imx: use generic name ele(EdgeLockSecure Enclave)
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index a0565f3..f43b73a 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -34,7 +34,7 @@
#include <asm/setup.h>
#include <asm/bootm.h>
#include <asm/arch-imx/cpu.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
#include <fuse.h>
#include <asm/arch/ddr.h>
@@ -151,7 +151,7 @@
return val;
}
-static void set_cpu_info(struct sentinel_get_info_data *info)
+static void set_cpu_info(struct ele_get_info_data *info)
{
gd->arch.soc_rev = info->soc;
gd->arch.lifecycle = info->lc;
@@ -557,7 +557,7 @@
struct udevice *devp;
int node, ret;
u32 res;
- struct sentinel_get_info_data info;
+ struct ele_get_info_data info;
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
@@ -568,7 +568,7 @@
if (gd->flags & GD_FLG_RELOC)
return 0;
- ret = ahab_get_info(&info, &res);
+ ret = ele_get_info(&info, &res);
if (ret)
return ret;
@@ -642,7 +642,7 @@
mem_id = SRC_MEM_MEDIA;
scr = BIT(5);
- /* Enable S400 handshake */
+ /* Enable ELE handshake */
struct blk_ctrl_s_aonmix_regs *s_regs =
(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
@@ -759,8 +759,8 @@
while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT))
val = readl(&mix_regs->func_stat);
- /* Release Sentinel TROUT */
- ahab_release_m33_trout();
+ /* Release ELE TROUT */
+ ele_release_m33_trout();
/* Mask WDOG1 IRQ from A55, we use it for M33 reset */
setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6));
@@ -768,7 +768,7 @@
/* Turn on WDOG1 clock */
ccm_lpcg_on(CCGR_WDG1, 1);
- /* Set sentinel LP handshake for M33 reset */
+ /* Set ELE LP handshake for M33 reset */
setbits_le32(&s_regs->lp_handshake[0], BIT(6));
/* Clear M33 TCM for ECC */