imx: use generic name ele(EdgeLockSecure Enclave)
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 99fc540..9bb3791 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -7,14 +7,13 @@
#include <command.h>
#include <errno.h>
#include <asm/io.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/image.h>
#include <console.h>
#include <cpu_func.h>
-#include <asm/mach-imx/ahab.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -267,7 +266,7 @@
flush_dcache_range(IMG_CONTAINER_BASE,
IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
- err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
+ err = ele_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
if (err) {
printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
err, resp);
@@ -282,7 +281,7 @@
int err;
u32 resp;
- err = ahab_release_container(&resp);
+ err = ele_release_container(&resp);
if (err) {
printf("Error: release container failed, resp 0x%x!\n", resp);
display_ahab_auth_ind(resp);
@@ -296,7 +295,7 @@
int err;
u32 resp;
- err = ahab_verify_image(image_index, &resp);
+ err = ele_verify_image(image_index, &resp);
if (err) {
printf("Authenticate img %d failed, return %d, resp 0x%x\n",
image_index, err, resp);
@@ -485,7 +484,7 @@
return -EPERM;
}
- err = ahab_forward_lifecycle(8, &resp);
+ err = ele_forward_lifecycle(8, &resp);
if (err != 0) {
printf("Error in forward lifecycle to OEM closed\n");
return -EIO;
@@ -502,7 +501,7 @@
int ret, i = 0;
do {
- ret = ahab_dump_buffer(buffer, 32);
+ ret = ele_dump_buffer(buffer, 32);
if (ret < 0) {
printf("Error in dump AHAB log\n");
return -EIO;
@@ -547,7 +546,7 @@
display_life_cycle(lc);
- ret = ahab_get_events(events, &cnt, NULL);
+ ret = ele_get_events(events, &cnt, NULL);
if (ret) {
printf("Get ELE EVENTS error %d\n", ret);
return CMD_RET_FAILURE;
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 50b097b..cfc09e7 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/mu_hal.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
#include <asm/arch/rdc.h>
#include <div64.h>
@@ -203,12 +203,12 @@
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x27020000UL;
- struct sentinel_msg msg;
+ struct ele_msg msg;
int ret;
u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
- msg.version = AHAB_VERSION;
- msg.tag = AHAB_CMD_TAG;
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
msg.size = 2;
msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
@@ -266,7 +266,7 @@
mrgd[4] |= ((access & 0xFFF) << 16);
}
- /* not handle other cases, since S400 only set ACCESS1 and 2 */
+ /* not handle other cases, since ELE only set ACCESS1 and 2 */
writel(mrgd[4], xrdc_base + off + 0x10);
return;
}
@@ -295,7 +295,7 @@
void xrdc_init_mrc(void)
{
- /* Re-config MRC3 for SRAM0 in case protected by S400 */
+ /* Re-config MRC3 for SRAM0 in case protected by ELE */
xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000);
xrdc_config_mrc_dx_perm(3, 0, 0, 1);
xrdc_config_mrc_dx_perm(3, 0, 1, 1);
@@ -320,7 +320,7 @@
xrdc_config_mrc_dx_perm(5, 0, 1, 1);
xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
- /* Set MRC6 for DDR access from Sentinel */
+ /* Set MRC6 for DDR access from ELE */
xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
xrdc_config_mrc_dx_perm(6, 0, 4, 1);
xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
@@ -404,7 +404,7 @@
val &= ~(0xFU << offset);
/* MBC0-3
- * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MBC0_MEMN_GLBAC0
*/
if (sec_access) {
@@ -445,7 +445,7 @@
continue;
/* MRC0,1
- * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MRCx_MEMN_GLBAC0
*/
if (sec_access) {
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 81eae02..e23cf60 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -14,7 +14,7 @@
#include <event.h>
#include <spl.h>
#include <asm/arch/rdc.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/mu_hal.h>
#include <cpu_func.h>
#include <asm/setup.h>
@@ -70,7 +70,7 @@
}
#endif
-static void set_cpu_info(struct sentinel_get_info_data *info)
+static void set_cpu_info(struct ele_get_info_data *info)
{
gd->arch.soc_rev = info->soc;
gd->arch.lifecycle = info->lc;
@@ -582,9 +582,9 @@
u32 res;
int ret;
- ret = ahab_read_common_fuse(1, uid, 4, &res);
+ ret = ele_read_common_fuse(1, uid, 4, &res);
if (ret)
- printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ printf("ele read fuse failed %d, 0x%x\n", ret, res);
else
printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2], uid[3]);
@@ -783,7 +783,7 @@
struct udevice *devp;
int ret;
u32 res;
- struct sentinel_get_info_data *info = (struct sentinel_get_info_data *)SRAM0_BASE;
+ struct ele_get_info_data *info = (struct ele_get_info_data *)SRAM0_BASE;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8ulp_mu), &devp);
if (ret) {
@@ -791,11 +791,11 @@
return ret;
}
- ret = ahab_get_info(info, &res);
+ ret = ele_get_info(info, &res);
if (ret) {
- printf("ahab_get_info failed %d\n", ret);
+ printf("ele_get_info failed %d\n", ret);
/* fallback to A0.1 revision */
- memset((void *)info, 0, sizeof(struct sentinel_get_info_data));
+ memset((void *)info, 0, sizeof(struct ele_get_info_data));
info->soc = 0xa000084d;
}
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index fcb02ed..b471a75 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -217,8 +217,8 @@
* CM33 Cache
* PowerQuad RAM
* ETF RAM
- * Sentinel PKC, Data RAM1, Inst RAM0/1
- * Sentinel ROM
+ * ELE PKC, Data RAM1, Inst RAM0/1
+ * ELE ROM
* uPower IRAM/DRAM
* uPower ROM
* CM33 ROM
@@ -230,7 +230,7 @@
* SSRAM Partition 7_a(128KB)
* SSRAM Partition 7_b(64KB)
* SSRAM Partition 7_c(64KB)
- * Sentinel Data RAM0, Inst RAM2
+ * ELE Data RAM0, Inst RAM2
*/
/* MIPI-CSI FIFO BIT28 not set */
memon = 0x3FFFFFEFFFFFFCUL;
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index a7eccca..766a881 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -709,8 +709,8 @@
/* Set A55 mtr bus to 133M */
{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
- /* Sentinel to 133M */
- {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+ /* ELE to 133M */
+ {ELE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_wakeup to 133M */
{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_AON to 133M */
@@ -740,8 +740,8 @@
{ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3},
/* Set A55 mtr bus to 133M */
{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
- /* Sentinel to 200M */
- {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
+ /* ELE to 200M */
+ {ELE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
/* Bus_wakeup to 133M */
{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_AON to 133M */
diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c
index 06b93f6..7d7ae86 100644
--- a/arch/arm/mach-imx/imx9/clock_root.c
+++ b/arch/arm/mach-imx/imx9/clock_root.c
@@ -34,7 +34,7 @@
{ ARM_A55_MTR_BUS_CLK_ROOT, 2 },
{ ARM_A55_CLK_ROOT, 0 },
{ M33_CLK_ROOT, 2 },
- { SENTINEL_CLK_ROOT, 2 },
+ { ELE_CLK_ROOT, 2 },
{ BUS_WAKEUP_CLK_ROOT, 2 },
{ BUS_AON_CLK_ROOT, 2 },
{ WAKEUP_AXI_CLK_ROOT, 0 },
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index a0565f3..f43b73a 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -34,7 +34,7 @@
#include <asm/setup.h>
#include <asm/bootm.h>
#include <asm/arch-imx/cpu.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
#include <fuse.h>
#include <asm/arch/ddr.h>
@@ -151,7 +151,7 @@
return val;
}
-static void set_cpu_info(struct sentinel_get_info_data *info)
+static void set_cpu_info(struct ele_get_info_data *info)
{
gd->arch.soc_rev = info->soc;
gd->arch.lifecycle = info->lc;
@@ -557,7 +557,7 @@
struct udevice *devp;
int node, ret;
u32 res;
- struct sentinel_get_info_data info;
+ struct ele_get_info_data info;
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
@@ -568,7 +568,7 @@
if (gd->flags & GD_FLG_RELOC)
return 0;
- ret = ahab_get_info(&info, &res);
+ ret = ele_get_info(&info, &res);
if (ret)
return ret;
@@ -642,7 +642,7 @@
mem_id = SRC_MEM_MEDIA;
scr = BIT(5);
- /* Enable S400 handshake */
+ /* Enable ELE handshake */
struct blk_ctrl_s_aonmix_regs *s_regs =
(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
@@ -759,8 +759,8 @@
while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT))
val = readl(&mix_regs->func_stat);
- /* Release Sentinel TROUT */
- ahab_release_m33_trout();
+ /* Release ELE TROUT */
+ ele_release_m33_trout();
/* Mask WDOG1 IRQ from A55, we use it for M33 reset */
setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6));
@@ -768,7 +768,7 @@
/* Turn on WDOG1 clock */
ccm_lpcg_on(CCGR_WDG1, 1);
- /* Set sentinel LP handshake for M33 reset */
+ /* Set ELE LP handshake for M33 reset */
setbits_le32(&s_regs->lp_handshake[0], BIT(6));
/* Clear M33 TCM for ECC */
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index e05c704..d0f855b 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -10,7 +10,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <div64.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/mu_hal.h>
#define DID_NUM 16
@@ -196,7 +196,7 @@
val &= ~(0xFU << offset);
/* MBC0-3
- * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MBC0_MEMN_GLBAC0
*/
if (sec_access) {
@@ -266,7 +266,7 @@
continue;
/* MRC0,1
- * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MRCx_MEMN_GLBAC0
*/
if (sec_access) {
@@ -315,7 +315,7 @@
int release_rdc(u8 xrdc)
{
ulong s_mu_base = 0x47520000UL;
- struct sentinel_msg msg;
+ struct ele_msg msg;
int ret;
u32 rdc_id;
@@ -336,8 +336,8 @@
return -EINVAL;
}
- msg.version = AHAB_VERSION;
- msg.tag = AHAB_CMD_TAG;
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
msg.size = 2;
msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */
@@ -394,7 +394,7 @@
/* DDR */
trdc_mrc_set_control(0x49010000, 0, 0, 0x7777);
- /* S400*/
+ /* ELE */
trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0);
/* MTR */