| commit | 5bc16d20321070e907601c88a84d5db96e40224e | [log] [tgz] |
|---|---|---|
| author | Jagan Teki <jagan@amarulasolutions.com> | Mon Dec 31 15:35:01 2018 +0530 |
| committer | Jagan Teki <jagan@amarulasolutions.com> | Fri Jan 18 22:19:09 2019 +0530 |
| tree | df491f67132d0a4ac89e6e71bebf9237098b0440 | |
| parent | b490aa57196a64b5d55fed1d29f1abe0aa08c562 [diff] |
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>