ARM: uniphier: remove sLD3 SoC support
This SoC is too old. It is difficult to maintain any longer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/mach-uniphier/spl_board_init.c b/arch/arm/mach-uniphier/spl_board_init.c
index 6da5631..1272b4e 100644
--- a/arch/arm/mach-uniphier/spl_board_init.c
+++ b/arch/arm/mach-uniphier/spl_board_init.c
@@ -24,35 +24,24 @@
};
static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- {
- .soc_id = UNIPHIER_SLD3_ID,
- .bcu_init = uniphier_sld3_bcu_init,
- .early_clk_init = uniphier_sld3_early_clk_init,
- .dpll_init = uniphier_sld3_dpll_init,
- .memconf_init = uniphier_memconf_3ch_no_disbit_init,
- .dram_clk_init = uniphier_sld3_dram_clk_init,
- .umc_init = uniphier_sld3_umc_init,
- },
-#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
{
.soc_id = UNIPHIER_LD4_ID,
.bcu_init = uniphier_ld4_bcu_init,
- .early_clk_init = uniphier_sld3_early_clk_init,
+ .early_clk_init = uniphier_ld4_early_clk_init,
.dpll_init = uniphier_ld4_dpll_init,
.memconf_init = uniphier_memconf_2ch_init,
- .dram_clk_init = uniphier_sld3_dram_clk_init,
+ .dram_clk_init = uniphier_ld4_dram_clk_init,
.umc_init = uniphier_ld4_umc_init,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
{
.soc_id = UNIPHIER_PRO4_ID,
- .early_clk_init = uniphier_sld3_early_clk_init,
+ .early_clk_init = uniphier_ld4_early_clk_init,
.dpll_init = uniphier_pro4_dpll_init,
.memconf_init = uniphier_memconf_2ch_init,
- .dram_clk_init = uniphier_sld3_dram_clk_init,
+ .dram_clk_init = uniphier_ld4_dram_clk_init,
.umc_init = uniphier_pro4_umc_init,
},
#endif
@@ -60,17 +49,17 @@
{
.soc_id = UNIPHIER_SLD8_ID,
.bcu_init = uniphier_ld4_bcu_init,
- .early_clk_init = uniphier_sld3_early_clk_init,
+ .early_clk_init = uniphier_ld4_early_clk_init,
.dpll_init = uniphier_sld8_dpll_init,
.memconf_init = uniphier_memconf_2ch_init,
- .dram_clk_init = uniphier_sld3_dram_clk_init,
+ .dram_clk_init = uniphier_ld4_dram_clk_init,
.umc_init = uniphier_sld8_umc_init,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
{
.soc_id = UNIPHIER_PRO5_ID,
- .early_clk_init = uniphier_sld3_early_clk_init,
+ .early_clk_init = uniphier_ld4_early_clk_init,
.dpll_init = uniphier_pro5_dpll_init,
.memconf_init = uniphier_memconf_2ch_init,
.dram_clk_init = uniphier_pro5_dram_clk_init,
@@ -80,7 +69,7 @@
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
{
.soc_id = UNIPHIER_PXS2_ID,
- .early_clk_init = uniphier_sld3_early_clk_init,
+ .early_clk_init = uniphier_ld4_early_clk_init,
.dpll_init = uniphier_pxs2_dpll_init,
.memconf_init = uniphier_memconf_3ch_init,
.dram_clk_init = uniphier_pxs2_dram_clk_init,
@@ -90,7 +79,7 @@
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{
.soc_id = UNIPHIER_LD6B_ID,
- .early_clk_init = uniphier_sld3_early_clk_init,
+ .early_clk_init = uniphier_ld4_early_clk_init,
.dpll_init = uniphier_pxs2_dpll_init,
.memconf_init = uniphier_memconf_3ch_init,
.dram_clk_init = uniphier_pxs2_dram_clk_init,