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git01.mediatek.com / filogic / uboot / d626ea478f07f4b847a6273f5ce4988f52857c2f / . / arch / arm / mach-uniphier / spl_board_init.c
blob: 6da5631bcacea588422ef29d24640e7f9ab68739 [file] [log] [blame]
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]1/*
2 * Copyright (C) 2015-2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <debug_uart.h>
10#include <spl.h>
11
12#include "init.h"
13#include "micro-support-card.h"
14#include "soc-info.h"
15
16struct uniphier_spl_initdata {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]17 unsigned int soc_id;
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]18 void (*bcu_init)(const struct uniphier_board_data *bd);
19 void (*early_clk_init)(void);
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]20 int (*dpll_init)(const struct uniphier_board_data *bd);
21 int (*memconf_init)(const struct uniphier_board_data *bd);
22 void (*dram_clk_init)(void);
23 int (*umc_init)(const struct uniphier_board_data *bd);
24};
25
26static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
27#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
28 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]29 .soc_id = UNIPHIER_SLD3_ID,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]30 .bcu_init = uniphier_sld3_bcu_init,
31 .early_clk_init = uniphier_sld3_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]32 .dpll_init = uniphier_sld3_dpll_init,
33 .memconf_init = uniphier_memconf_3ch_no_disbit_init,
34 .dram_clk_init = uniphier_sld3_dram_clk_init,
35 .umc_init = uniphier_sld3_umc_init,
36 },
37#endif
38#if defined(CONFIG_ARCH_UNIPHIER_LD4)
39 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]40 .soc_id = UNIPHIER_LD4_ID,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]41 .bcu_init = uniphier_ld4_bcu_init,
42 .early_clk_init = uniphier_sld3_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]43 .dpll_init = uniphier_ld4_dpll_init,
44 .memconf_init = uniphier_memconf_2ch_init,
45 .dram_clk_init = uniphier_sld3_dram_clk_init,
46 .umc_init = uniphier_ld4_umc_init,
47 },
48#endif
49#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
50 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]51 .soc_id = UNIPHIER_PRO4_ID,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]52 .early_clk_init = uniphier_sld3_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]53 .dpll_init = uniphier_pro4_dpll_init,
54 .memconf_init = uniphier_memconf_2ch_init,
55 .dram_clk_init = uniphier_sld3_dram_clk_init,
56 .umc_init = uniphier_pro4_umc_init,
57 },
58#endif
59#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
60 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]61 .soc_id = UNIPHIER_SLD8_ID,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]62 .bcu_init = uniphier_ld4_bcu_init,
63 .early_clk_init = uniphier_sld3_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]64 .dpll_init = uniphier_sld8_dpll_init,
65 .memconf_init = uniphier_memconf_2ch_init,
66 .dram_clk_init = uniphier_sld3_dram_clk_init,
67 .umc_init = uniphier_sld8_umc_init,
68 },
69#endif
70#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
71 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]72 .soc_id = UNIPHIER_PRO5_ID,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]73 .early_clk_init = uniphier_sld3_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]74 .dpll_init = uniphier_pro5_dpll_init,
75 .memconf_init = uniphier_memconf_2ch_init,
76 .dram_clk_init = uniphier_pro5_dram_clk_init,
77 .umc_init = uniphier_pro5_umc_init,
78 },
79#endif
80#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
81 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]82 .soc_id = UNIPHIER_PXS2_ID,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]83 .early_clk_init = uniphier_sld3_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]84 .dpll_init = uniphier_pxs2_dpll_init,
85 .memconf_init = uniphier_memconf_3ch_init,
86 .dram_clk_init = uniphier_pxs2_dram_clk_init,
87 .umc_init = uniphier_pxs2_umc_init,
88 },
89#endif
90#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
91 {
Masahiro Yamada31649052017-01-21 18:05:26 +0900[diff] [blame]92 .soc_id = UNIPHIER_LD6B_ID,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]93 .early_clk_init = uniphier_sld3_early_clk_init,
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]94 .dpll_init = uniphier_pxs2_dpll_init,
95 .memconf_init = uniphier_memconf_3ch_init,
96 .dram_clk_init = uniphier_pxs2_dram_clk_init,
97 .umc_init = uniphier_pxs2_umc_init,
98 },
99#endif
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]100};
Masahiro Yamada1b818982017-01-21 18:05:27 +0900[diff] [blame]101UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata)
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]102
103void spl_board_init(void)
104{
105 const struct uniphier_board_data *bd;
106 const struct uniphier_spl_initdata *initdata;
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]107 int ret;
108
109#ifdef CONFIG_DEBUG_UART
110 debug_uart_init();
111#endif
112
113 bd = uniphier_get_board_param();
114 if (!bd)
115 hang();
116
Masahiro Yamada1b818982017-01-21 18:05:27 +0900[diff] [blame]117 initdata = uniphier_get_spl_initdata();
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]118 if (!initdata)
119 hang();
120
121 if (initdata->bcu_init)
122 initdata->bcu_init(bd);
123
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]124 initdata->early_clk_init();
125
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]126#ifdef CONFIG_SPL_SERIAL_SUPPORT
127 preloader_console_init();
128#endif
129
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]130 ret = initdata->dpll_init(bd);
131 if (ret) {
132 pr_err("failed to init DPLL\n");
133 hang();
134 }
135
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]136 ret = initdata->memconf_init(bd);
137 if (ret) {
138 pr_err("failed to init MEMCONF\n");
139 hang();
140 }
141
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]142 initdata->dram_clk_init();
143
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]144 ret = initdata->umc_init(bd);
145 if (ret) {
146 pr_err("failed to init DRAM\n");
147 hang();
148 }
Masahiro Yamada8c3aa6b2017-01-15 14:59:09 +0900[diff] [blame]149}