| /* |
| * (C) Copyright 2010 |
| * Texas Instruments Incorporated. |
| * Aneesh V <aneesh@ti.com> |
| * Steve Sakoman <steve@sakoman.com> |
| * |
| * Configuration settings for the TI SDP4430 board. |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| #ifndef __CONFIG_H |
| #define __CONFIG_H |
| |
| /* |
| * High Level Configuration Options |
| */ |
| #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ |
| #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
| #define CONFIG_OMAP44XX 1 /* which is a 44XX */ |
| #define CONFIG_OMAP4430 1 /* which is in a 4430 */ |
| #define CONFIG_4430SDP 1 /* working with SDP */ |
| #define CONFIG_ARCH_CPU_INIT |
| |
| /* Get CPU defs */ |
| #include <asm/arch/cpu.h> |
| #include <asm/arch/omap4.h> |
| |
| /* Display CPU and Board Info */ |
| #define CONFIG_DISPLAY_CPUINFO 1 |
| #define CONFIG_DISPLAY_BOARDINFO 1 |
| |
| /* Clock Defines */ |
| #define V_OSCK 38400000 /* Clock output from T2 */ |
| #define V_SCLK V_OSCK |
| |
| #undef CONFIG_USE_IRQ /* no support for IRQs */ |
| #define CONFIG_MISC_INIT_R |
| |
| #define CONFIG_OF_LIBFDT 1 |
| |
| #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| #define CONFIG_SETUP_MEMORY_TAGS 1 |
| #define CONFIG_INITRD_TAG 1 |
| #define CONFIG_REVISION_TAG 1 |
| |
| /* |
| * Size of malloc() pool |
| * Total Size Environment - 128k |
| * Malloc - add 256k |
| */ |
| #define CONFIG_ENV_SIZE (128 << 10) |
| #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) |
| /* Vector Base */ |
| #define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE |
| |
| /* |
| * Hardware drivers |
| */ |
| |
| /* |
| * serial port - NS16550 compatible |
| */ |
| #define V_NS16550_CLK 48000000 |
| |
| #define CONFIG_SYS_NS16550 |
| #define CONFIG_SYS_NS16550_SERIAL |
| #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
| #define CONFIG_CONS_INDEX 3 |
| #define CONFIG_SYS_NS16550_COM3 UART3_BASE |
| |
| #define CONFIG_BAUDRATE 115200 |
| #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
| 115200} |
| /* I2C */ |
| #define CONFIG_HARD_I2C 1 |
| #define CONFIG_SYS_I2C_SPEED 100000 |
| #define CONFIG_SYS_I2C_SLAVE 1 |
| #define CONFIG_SYS_I2C_BUS 0 |
| #define CONFIG_SYS_I2C_BUS_SELECT 1 |
| #define CONFIG_DRIVER_OMAP34XX_I2C 1 |
| #define CONFIG_I2C_MULTI_BUS 1 |
| |
| /* TWL6030 */ |
| #define CONFIG_TWL6030_POWER 1 |
| #define CONFIG_CMD_BAT 1 |
| |
| /* MMC */ |
| #define CONFIG_GENERIC_MMC 1 |
| #define CONFIG_MMC 1 |
| #define CONFIG_OMAP_HSMMC 1 |
| #define CONFIG_SYS_MMC_SET_DEV 1 |
| #define CONFIG_DOS_PARTITION 1 |
| |
| /* MMC ENV related defines */ |
| #define CONFIG_ENV_IS_IN_MMC 1 |
| #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ |
| #define CONFIG_ENV_OFFSET 0xE0000 |
| |
| /* USB */ |
| #define CONFIG_MUSB_UDC 1 |
| #define CONFIG_USB_OMAP3 1 |
| |
| /* USB device configuration */ |
| #define CONFIG_USB_DEVICE 1 |
| #define CONFIG_USB_TTY 1 |
| #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
| |
| /* Flash */ |
| #define CONFIG_SYS_NO_FLASH 1 |
| |
| /* commands to include */ |
| #include <config_cmd_default.h> |
| |
| /* Enabled commands */ |
| #define CONFIG_CMD_EXT2 /* EXT2 Support */ |
| #define CONFIG_CMD_FAT /* FAT support */ |
| #define CONFIG_CMD_I2C /* I2C serial bus support */ |
| #define CONFIG_CMD_MMC /* MMC support */ |
| #define CONFIG_CMD_SAVEENV |
| |
| /* Disabled commands */ |
| #undef CONFIG_CMD_NET |
| #undef CONFIG_CMD_NFS |
| #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ |
| #undef CONFIG_CMD_IMLS /* List all found images */ |
| |
| /* |
| * Environment setup |
| */ |
| |
| #define CONFIG_BOOTDELAY 3 |
| |
| #define CONFIG_ENV_OVERWRITE |
| |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| "loadaddr=0x82000000\0" \ |
| "console=ttyS2,115200n8\0" \ |
| "usbtty=cdc_acm\0" \ |
| "vram=16M\0" \ |
| "mmcdev=0\0" \ |
| "mmcroot=/dev/mmcblk0p2 rw\0" \ |
| "mmcrootfstype=ext3 rootwait\0" \ |
| "mmcargs=setenv bootargs console=${console} " \ |
| "vram=${vram} " \ |
| "root=${mmcroot} " \ |
| "rootfstype=${mmcrootfstype}\0" \ |
| "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
| "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ |
| "source ${loadaddr}\0" \ |
| "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
| "mmcboot=echo Booting from mmc${mmcdev} ...; " \ |
| "run mmcargs; " \ |
| "bootm ${loadaddr}\0" \ |
| |
| #define CONFIG_BOOTCOMMAND \ |
| "if mmc rescan ${mmcdev}; then " \ |
| "if run loadbootscript; then " \ |
| "run bootscript; " \ |
| "else " \ |
| "if run loaduimage; then " \ |
| "run mmcboot; " \ |
| "fi; " \ |
| "fi; " \ |
| "fi" |
| |
| #define CONFIG_AUTO_COMPLETE 1 |
| |
| /* |
| * Miscellaneous configurable options |
| */ |
| |
| #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
| #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| #define CONFIG_SYS_PROMPT "OMAP4430 SDP # " |
| #define CONFIG_SYS_CBSIZE 256 |
| /* Print Buffer Size */ |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| sizeof(CONFIG_SYS_PROMPT) + 16) |
| #define CONFIG_SYS_MAXARGS 16 |
| /* Boot Argument Buffer Size */ |
| #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
| |
| /* |
| * memtest setup |
| */ |
| #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) |
| |
| /* Default load address */ |
| #define CONFIG_SYS_LOAD_ADDR 0x80000000 |
| |
| /* Use General purpose timer 1 */ |
| #define CONFIG_SYS_TIMERBASE GPT2_BASE |
| #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
| #define CONFIG_SYS_HZ 1000 |
| |
| /* |
| * Stack sizes |
| * |
| * The stack sizes are set up in start.S using the settings below |
| */ |
| #define CONFIG_STACKSIZE (128 << 10) /* Regular stack */ |
| #ifdef CONFIG_USE_IRQ |
| #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */ |
| #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */ |
| #endif |
| |
| /* |
| * SDRAM Memory Map |
| * Even though we use two CS all the memory |
| * is mapped to one contiguous block |
| */ |
| #define CONFIG_NR_DRAM_BANKS 1 |
| |
| #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
| #define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800 |
| #define CONFIG_SYS_INIT_RAM_SIZE 0x800 |
| #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| CONFIG_SYS_INIT_RAM_SIZE - \ |
| GENERATED_GBL_DATA_SIZE) |
| |
| #ifndef CONFIG_SYS_L2CACHE_OFF |
| #define CONFIG_SYS_L2_PL310 1 |
| #define CONFIG_SYS_PL310_BASE 0x48242000 |
| #endif |
| |
| /* Defines for SDRAM init */ |
| #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
| #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION |
| #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS |
| #endif |
| |
| #endif /* __CONFIG_H */ |