| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2018 NXP |
| */ |
| |
| #include <common.h> |
| #include <errno.h> |
| #include <linux/libfdt.h> |
| #include <environment.h> |
| #include <asm/io.h> |
| #include <asm/gpio.h> |
| #include <asm/arch/clock.h> |
| #include <asm/arch/sci/sci.h> |
| #include <asm/arch/imx8-pins.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/sys_proto.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ |
| (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ |
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ |
| (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) |
| |
| static iomux_cfg_t uart0_pads[] = { |
| SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static void setup_iomux_uart(void) |
| { |
| imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); |
| } |
| |
| int board_early_init_f(void) |
| { |
| int ret; |
| /* Set UART0 clock root to 80 MHz */ |
| sc_pm_clock_rate_t rate = 80000000; |
| |
| /* Power up UART0 */ |
| ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); |
| if (ret) |
| return ret; |
| |
| ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); |
| if (ret) |
| return ret; |
| |
| /* Enable UART0 clock root */ |
| ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); |
| if (ret) |
| return ret; |
| |
| setup_iomux_uart(); |
| |
| sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); |
| |
| return 0; |
| } |
| |
| #if IS_ENABLED(CONFIG_DM_GPIO) |
| static void board_gpio_init(void) |
| { |
| /* TODO */ |
| } |
| #else |
| static inline void board_gpio_init(void) {} |
| #endif |
| |
| #if IS_ENABLED(CONFIG_FEC_MXC) |
| #include <miiphy.h> |
| |
| int board_phy_config(struct phy_device *phydev) |
| { |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); |
| |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); |
| |
| if (phydev->drv->config) |
| phydev->drv->config(phydev); |
| |
| return 0; |
| } |
| #endif |
| |
| void build_info(void) |
| { |
| u32 sc_build = 0, sc_commit = 0; |
| |
| /* Get SCFW build and commit id */ |
| sc_misc_build_info(-1, &sc_build, &sc_commit); |
| if (!sc_build) { |
| printf("SCFW does not support build info\n"); |
| sc_commit = 0; /* Display 0 when the build info is not supported*/ |
| } |
| printf("Build: SCFW %x\n", sc_commit); |
| } |
| |
| int checkboard(void) |
| { |
| puts("Board: iMX8QM MEK\n"); |
| |
| build_info(); |
| print_bootinfo(); |
| |
| return 0; |
| } |
| |
| int board_init(void) |
| { |
| /* Power up base board */ |
| sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON); |
| |
| board_gpio_init(); |
| |
| return 0; |
| } |
| |
| void detail_board_ddr_info(void) |
| { |
| puts("\nDDR "); |
| } |
| |
| /* |
| * Board specific reset that is system reset. |
| */ |
| void reset_cpu(ulong addr) |
| { |
| /* TODO */ |
| } |
| |
| #ifdef CONFIG_OF_BOARD_SETUP |
| int ft_board_setup(void *blob, bd_t *bd) |
| { |
| return 0; |
| } |
| #endif |
| |
| int board_mmc_get_env_dev(int devno) |
| { |
| return devno; |
| } |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| env_set("board_name", "MEK"); |
| env_set("board_rev", "iMX8QM"); |
| #endif |
| |
| return 0; |
| } |